63 lines
3.6 KiB
JSON
63 lines
3.6 KiB
JSON
{
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"timestamp_utc": "2026-04-19T06:38:06.434830+00:00",
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"repo_root": "/Users/ningyedong/Coding/Verilog-Learn",
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"workspace": "/private/tmp/chipverify_github_cpu_example",
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"projects_file": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/projects.json",
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"tool": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py",
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"results": [
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{
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"name": "ultraembedded_riscv_core",
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"repo": "https://github.com/ultraembedded/riscv.git",
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"stars": 1703,
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"status": "pass",
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"clone_status": "updated",
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"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv",
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"top": "riscv_core",
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"return_code": 0,
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"artifacts": {
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"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v",
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"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd",
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"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log",
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"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out",
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"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/run.log"
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}
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{
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"name": "zipcpu",
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"stars": 1535,
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"status": "pass",
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"clone_status": "cloned",
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"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl",
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"top": "zipcore",
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"artifacts": {
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"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v",
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"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log",
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"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out",
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"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/run.log"
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}
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},
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{
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"name": "e203_cpu_top_fullrtl",
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"repo": "https://github.com/riscv-mcu/e203_hbirdv2.git",
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"stars": 1811,
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"status": "pass",
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"clone_status": "cloned",
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"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl",
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"top": "e203_cpu_top",
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"return_code": 0,
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"artifacts": {
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"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v",
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"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd",
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"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log",
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"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out",
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"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/run.log"
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}
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}
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],
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"pass_count": 3,
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"fail_count": 0,
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"total": 3
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} |