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SLWChipVerify/auto_single_check/sim_output.log
2026-04-19 16:14:05 +08:00

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VCD info: dumpfile simple_cpu_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_single_check/tb_simple_cpu_auto.v:27: $finish called at 76000 (1ps)