3 lines
180 B
Plaintext
3 lines
180 B
Plaintext
VCD info: dumpfile simple_cpu_auto.vcd opened for output.
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/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_out_cli/tb_simple_cpu_auto.v:27: $finish called at 136000 (1ps)
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