21 lines
992 B
JSON
21 lines
992 B
JSON
{
|
|
"timestamp": "2026-04-19T14:24:11",
|
|
"project_dir": "/Users/ningyedong/Coding/Verilog-Learn/simple_cpu",
|
|
"output_dir": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch",
|
|
"total_candidates": 1,
|
|
"passed": 1,
|
|
"failed": 0,
|
|
"results": [
|
|
{
|
|
"module": "simple_cpu",
|
|
"module_file": "/Users/ningyedong/Coding/Verilog-Learn/simple_cpu/simple_cpu.v",
|
|
"output_dir": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu",
|
|
"status": "pass",
|
|
"tb_path": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/tb_simple_cpu_auto.v",
|
|
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/auto_sim.out",
|
|
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/sim_output.log",
|
|
"vcd_path": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/simple_cpu_auto.vcd",
|
|
"error": null
|
|
}
|
|
]
|
|
} |