18 lines
1.2 KiB
Plaintext
18 lines
1.2 KiB
Plaintext
COMMAND:
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/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl --top zipcore --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu --cycles 12 --period 10 --reset-cycles 2
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STDOUT:
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=== ChipVerify One-Click Auto Verification ===
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Found 51 Verilog files
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Selected top module: zipcore
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Top module file: /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl/core/zipcore.v
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Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v
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Simulation completed successfully
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Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out
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Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
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Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log
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Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
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STDERR:
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