63 lines
660 B
Plaintext
63 lines
660 B
Plaintext
$date
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Sun Apr 19 14:24:36 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_simple_cpu_auto $end
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$var reg 1 ! clk $end
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$var reg 1 " rst $end
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$var integer 32 # i [31:0] $end
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$var integer 32 $ seed [31:0] $end
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$scope module dut $end
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$var wire 1 ! clk $end
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$var wire 1 " rst $end
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$var reg 4 % cnt [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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b0 %
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b1001101010010011001000011 $
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bx #
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1"
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0!
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$end
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#5000
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b1 %
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b0 #
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0"
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1!
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#10000
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0!
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#15000
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b10 %
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b1 #
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1!
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#20000
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0!
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#25000
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b11 %
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b10 #
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1!
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#30000
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0!
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#35000
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b100 %
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b11 #
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1!
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#40000
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0!
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#45000
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b101 %
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b100 #
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1!
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#46000
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