30 lines
563 B
Verilog
30 lines
563 B
Verilog
`timescale 1ns/1ps
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module tb_simple_cpu_auto;
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reg clk;
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reg rst;
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integer i;
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integer seed;
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simple_cpu dut (.clk(clk), .rst(rst));
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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initial begin
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seed = 20260419;
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$dumpfile("simple_cpu_auto.vcd");
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$dumpvars(0, tb_simple_cpu_auto);
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rst = 1'b1;
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repeat (2) @(posedge clk);
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rst = 1'b0;
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for (i = 0; i < 20; i = i + 1) begin
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@(posedge clk);
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end
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#1;
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$finish;
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end
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endmodule
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