163 lines
1.2 KiB
Plaintext
163 lines
1.2 KiB
Plaintext
$date
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Sun Apr 19 14:11:03 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_simple_cpu_auto $end
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$var reg 1 ! clk $end
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$var reg 1 " rst $end
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$var integer 32 # i [31:0] $end
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$var integer 32 $ seed [31:0] $end
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$scope module dut $end
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$var wire 1 ! clk $end
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$var wire 1 " rst $end
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$var reg 4 % cnt [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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b0 %
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b1001101010010011001000011 $
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bx #
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1"
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0!
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$end
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#5000
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1!
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#10000
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0!
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#15000
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b1 %
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b0 #
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0"
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1!
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#20000
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0!
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#25000
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b10 %
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b1 #
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1!
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#30000
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0!
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#35000
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b11 %
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b10 #
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1!
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#40000
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0!
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#45000
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b100 %
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b11 #
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1!
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#50000
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0!
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#55000
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b101 %
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b100 #
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1!
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#60000
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0!
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#65000
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b110 %
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b101 #
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1!
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#70000
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0!
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#75000
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b111 %
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b110 #
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1!
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#80000
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0!
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#85000
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b1000 %
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b111 #
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1!
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#90000
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0!
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#95000
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b1001 %
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b1000 #
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1!
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#100000
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0!
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#105000
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b1010 %
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b1001 #
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1!
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#110000
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0!
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#115000
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b1011 %
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b1010 #
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1!
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#120000
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0!
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#125000
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b1100 %
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b1011 #
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1!
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#130000
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0!
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#135000
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b1101 %
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b1100 #
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1!
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#140000
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0!
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#145000
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b1110 %
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b1101 #
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1!
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#150000
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0!
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#155000
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b1111 %
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b1110 #
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1!
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#160000
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0!
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#165000
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b0 %
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b1111 #
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1!
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#170000
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0!
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#175000
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b1 %
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b10000 #
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1!
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#180000
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0!
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#185000
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b10 %
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b10001 #
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1!
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#190000
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0!
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#195000
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b11 %
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b10010 #
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1!
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#200000
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0!
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#205000
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b100 %
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b10011 #
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1!
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#210000
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0!
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#215000
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b101 %
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b10100 #
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1!
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#216000
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