101 lines
3.2 KiB
Plaintext
101 lines
3.2 KiB
Plaintext
#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
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:ivl_version "13.0 (stable)" "(v13_0)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
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S_0x1012a3bb0 .scope package, "$unit" "$unit" 2 1;
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.timescale 0 0;
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S_0x1012a2190 .scope module, "tb_simple_cpu_auto" "tb_simple_cpu_auto" 3 2;
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.timescale -9 -12;
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v0x1012a84e0_0 .var "clk", 0 0;
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v0x1012a8580_0 .var/i "i", 31 0;
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v0x1012a8620_0 .var "rst", 0 0;
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v0x1012a86c0_0 .var/i "seed", 31 0;
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E_0x1012a7830 .event posedge, v0x1012a0d80_0;
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S_0x1012a2310 .scope module, "dut" "simple_cpu" 3 9, 4 1 0, S_0x1012a2190;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clk";
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.port_info 1 /INPUT 1 "rst";
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v0x1012a0d80_0 .net "clk", 0 0, v0x1012a84e0_0; 1 drivers
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v0x1012a0f70_0 .var "cnt", 3 0;
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v0x1012a8440_0 .net "rst", 0 0, v0x1012a8620_0; 1 drivers
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E_0x1012a2680 .event posedge, v0x1012a8440_0, v0x1012a0d80_0;
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.scope S_0x1012a2310;
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T_0 ;
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%wait E_0x1012a2680;
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%load/vec4 v0x1012a8440_0;
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%flag_set/vec4 8;
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%jmp/0xz T_0.0, 8;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x1012a0f70_0, 0;
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%jmp T_0.1;
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T_0.0 ;
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%load/vec4 v0x1012a0f70_0;
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%addi 1, 0, 4;
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%assign/vec4 v0x1012a0f70_0, 0;
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T_0.1 ;
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%jmp T_0;
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.thread T_0;
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.scope S_0x1012a2190;
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T_1 ;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x1012a84e0_0, 0, 1;
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T_1.0 ;
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%delay 5000, 0;
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%load/vec4 v0x1012a84e0_0;
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%inv;
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%store/vec4 v0x1012a84e0_0, 0, 1;
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%jmp T_1.0;
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T_1.1 ;
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%end;
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.thread T_1;
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.scope S_0x1012a2190;
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T_2 ;
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%pushi/vec4 20260419, 0, 32;
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%store/vec4 v0x1012a86c0_0, 0, 32;
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%vpi_call/w 3 18 "$dumpfile", "simple_cpu_auto.vcd" {0 0 0};
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%vpi_call/w 3 19 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1012a2190 {0 0 0};
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x1012a8620_0, 0, 1;
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%pushi/vec4 2, 0, 32;
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T_2.0 %dup/vec4;
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%cmpi/s 0, 0, 32;
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%jmp/1xz T_2.1, 5;
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%jmp/1 T_2.1, 4;
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%subi 1, 0, 32;
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%wait E_0x1012a7830;
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%jmp T_2.0;
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T_2.1 ;
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%pop/vec4 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x1012a8620_0, 0, 1;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x1012a8580_0, 0, 32;
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T_2.2 ; Top of for-loop
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%load/vec4 v0x1012a8580_0;
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%cmpi/s 8, 0, 32;
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%jmp/0xz T_2.3, 5;
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%wait E_0x1012a7830;
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T_2.4 ; for-loop step statement
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%load/vec4 v0x1012a8580_0;
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%addi 1, 0, 32;
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%store/vec4 v0x1012a8580_0, 0, 32;
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%jmp T_2.2;
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T_2.3 ; for-loop exit label
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%delay 1000, 0;
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%vpi_call/w 3 27 "$finish" {0 0 0};
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%end;
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.thread T_2;
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# The file index is used to find the file name in the following table.
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:file_names 5;
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"N/A";
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"<interactive>";
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"-";
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"/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/tb_simple_cpu_auto.v";
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"/Users/ningyedong/Coding/Verilog-Learn/simple_cpu/simple_cpu.v";
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