`timescale 1ns/1ps
module tb_simple_cpu_auto;

    reg clk;
    reg rst;
    integer i;
    integer seed;

    simple_cpu dut (.clk(clk), .rst(rst));

    initial begin
        clk = 1'b0;
        forever #5 clk = ~clk;
    end

    initial begin
        seed = 20260419;
        $dumpfile("simple_cpu_auto.vcd");
        $dumpvars(0, tb_simple_cpu_auto);
        rst = 1'b1;
        repeat (2) @(posedge clk);
        rst = 1'b0;
        for (i = 0; i < 20; i = i + 1) begin
            @(posedge clk);
        end
        #1;
        $finish;
    end
endmodule