$date
	Sun Apr 19 14:11:03 2026
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module tb_simple_cpu_auto $end
$var reg 1 ! clk $end
$var reg 1 " rst $end
$var integer 32 # i [31:0] $end
$var integer 32 $ seed [31:0] $end
$scope module dut $end
$var wire 1 ! clk $end
$var wire 1 " rst $end
$var reg 4 % cnt [3:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
b0 %
b1001101010010011001000011 $
bx #
1"
0!
$end
#5000
1!
#10000
0!
#15000
b1 %
b0 #
0"
1!
#20000
0!
#25000
b10 %
b1 #
1!
#30000
0!
#35000
b11 %
b10 #
1!
#40000
0!
#45000
b100 %
b11 #
1!
#50000
0!
#55000
b101 %
b100 #
1!
#60000
0!
#65000
b110 %
b101 #
1!
#70000
0!
#75000
b111 %
b110 #
1!
#80000
0!
#85000
b1000 %
b111 #
1!
#90000
0!
#95000
b1001 %
b1000 #
1!
#100000
0!
#105000
b1010 %
b1001 #
1!
#110000
0!
#115000
b1011 %
b1010 #
1!
#120000
0!
#125000
b1100 %
b1011 #
1!
#130000
0!
#135000
b1101 %
b1100 #
1!
#140000
0!
#145000
b1110 %
b1101 #
1!
#150000
0!
#155000
b1111 %
b1110 #
1!
#160000
0!
#165000
b0 %
b1111 #
1!
#170000
0!
#175000
b1 %
b10000 #
1!
#180000
0!
#185000
b10 %
b10001 #
1!
#190000
0!
#195000
b11 %
b10010 #
1!
#200000
0!
#205000
b100 %
b10011 #
1!
#210000
0!
#215000
b101 %
b10100 #
1!
#216000