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examples/simple_cpu_seq_spec.json

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+{
+  "kind": "sequential",
+  "clock": {
+    "name": "clk",
+    "period_ns": 10,
+    "initial": 0
+  },
+  "reset": {
+    "name": "rst",
+    "active": 1,
+    "cycles": 2
+  },
+  "inputs": [],
+  "outputs": [],
+  "observes": [
+    {
+      "name": "cnt",
+      "expr": "dut.cnt",
+      "width": 4
+    }
+  ],
+  "max_cycles": 6,
+  "auto_stimulus": {
+    "enabled": false
+  },
+  "assertions": [
+    {
+      "name": "reset_cycle0",
+      "cycle": 0,
+      "expect": {
+        "cnt": 0
+      }
+    },
+    {
+      "name": "reset_cycle1",
+      "cycle": 1,
+      "expect": {
+        "cnt": 0
+      }
+    },
+    {
+      "name": "count_cycle2",
+      "cycle": 2,
+      "expect": {
+        "cnt": 1
+      }
+    },
+    {
+      "name": "count_cycle3",
+      "cycle": 3,
+      "expect": {
+        "cnt": 2
+      }
+    },
+    {
+      "name": "count_cycle4",
+      "cycle": 4,
+      "expect": {
+        "cnt": 3
+      }
+    }
+  ]
+}