ningyd/SLWChipVerify
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ningyd
2026-04-19 16:14:05 +08:00
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examples/github_cpu_validation/results/zipcpu/sim_output.log Normal file
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VCD info: dumpfile zipcore_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v:106: $finish called at 136000 (1ps)