Init Push

examples/github_cpu_validation/results/zipcpu/run.log

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+COMMAND:
+/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl --top zipcore --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu --cycles 12 --period 10 --reset-cycles 2
+
+STDOUT:
+=== ChipVerify One-Click Auto Verification ===
+Found 51 Verilog files
+Selected top module: zipcore
+Top module file: /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl/core/zipcore.v
+Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v
+Simulation completed successfully
+Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out
+Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
+Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log
+Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
+
+
+STDERR:

examples/github_cpu_validation/results/zipcpu/sim_output.log

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+VCD info: dumpfile zipcore_auto.vcd opened for output.
+/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v:106: $finish called at 136000 (1ps)

examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v

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+`timescale 1ns/1ps
+module tb_zipcore_auto;
+
+    reg i_clk;
+    reg i_reset;
+    reg i_interrupt;
+    reg i_halt;
+    reg i_clear_cache;
+    reg [4:0] i_dbg_wreg;
+    reg i_dbg_we;
+    reg [31:0] i_dbg_data;
+    reg [4:0] i_dbg_rreg;
+    reg i_pf_valid;
+    reg i_pf_illegal;
+    reg [31:0] i_pf_instruction;
+    reg i_pf_instruction_pc;
+    reg i_mem_busy;
+    reg i_mem_rdbusy;
+    reg i_mem_pipe_stalled;
+    reg i_mem_valid;
+    reg i_bus_err;
+    reg [4:0] i_mem_wreg;
+    reg [31:0] i_mem_result;
+    wire o_clken;
+    wire o_dbg_stall;
+    wire [31:0] o_dbg_reg;
+    wire [2:0] o_dbg_cc;
+    wire o_break;
+    wire o_pf_new_pc;
+    wire o_clear_icache;
+    wire o_pf_ready;
+    wire o_pf_request_address;
+    wire o_clear_dcache;
+    wire o_mem_ce;
+    wire o_bus_lock;
+    wire [2:0] o_mem_op;
+    wire [31:0] o_mem_addr;
+    wire [31:0] o_mem_data;
+    wire o_mem_lock_pc;
+    wire [4:0] o_mem_reg;
+    wire o_op_stall;
+    wire o_pf_stall;
+    wire o_i_count;
+    wire [31:0] o_debug;
+    wire o_prof_stb;
+    wire o_prof_addr;
+    wire [31:0] o_prof_ticks;
+    integer i;
+    integer seed;
+
+    zipcore dut (.i_clk(i_clk), .i_reset(i_reset), .i_interrupt(i_interrupt), .o_clken(o_clken), .i_halt(i_halt), .i_clear_cache(i_clear_cache), .i_dbg_wreg(i_dbg_wreg), .i_dbg_we(i_dbg_we), .i_dbg_data(i_dbg_data), .i_dbg_rreg(i_dbg_rreg), .o_dbg_stall(o_dbg_stall), .o_dbg_reg(o_dbg_reg), .o_dbg_cc(o_dbg_cc), .o_break(o_break), .o_pf_new_pc(o_pf_new_pc), .o_clear_icache(o_clear_icache), .o_pf_ready(o_pf_ready), .o_pf_request_address(o_pf_request_address), .i_pf_valid(i_pf_valid), .i_pf_illegal(i_pf_illegal), .i_pf_instruction(i_pf_instruction), .i_pf_instruction_pc(i_pf_instruction_pc), .o_clear_dcache(o_clear_dcache), .o_mem_ce(o_mem_ce), .o_bus_lock(o_bus_lock), .o_mem_op(o_mem_op), .o_mem_addr(o_mem_addr), .o_mem_data(o_mem_data), .o_mem_lock_pc(o_mem_lock_pc), .o_mem_reg(o_mem_reg), .i_mem_busy(i_mem_busy), .i_mem_rdbusy(i_mem_rdbusy), .i_mem_pipe_stalled(i_mem_pipe_stalled), .i_mem_valid(i_mem_valid), .i_bus_err(i_bus_err), .i_mem_wreg(i_mem_wreg), .i_mem_result(i_mem_result), .o_op_stall(o_op_stall), .o_pf_stall(o_pf_stall), .o_i_count(o_i_count), .o_debug(o_debug), .o_prof_stb(o_prof_stb), .o_prof_addr(o_prof_addr), .o_prof_ticks(o_prof_ticks));
+
+    initial begin
+        i_clk = 1'b0;
+        forever #5 i_clk = ~i_clk;
+    end
+
+    initial begin
+        seed = 20260419;
+        $dumpfile("zipcore_auto.vcd");
+        $dumpvars(0, tb_zipcore_auto);
+        i_interrupt = 1'd0;
+        i_halt = 1'd0;
+        i_clear_cache = 1'd0;
+        i_dbg_wreg = 5'd0;
+        i_dbg_we = 1'd0;
+        i_dbg_data = 32'd0;
+        i_dbg_rreg = 5'd0;
+        i_pf_valid = 1'd0;
+        i_pf_illegal = 1'd0;
+        i_pf_instruction = 32'd0;
+        i_pf_instruction_pc = 1'd0;
+        i_mem_busy = 1'd0;
+        i_mem_rdbusy = 1'd0;
+        i_mem_pipe_stalled = 1'd0;
+        i_mem_valid = 1'd0;
+        i_bus_err = 1'd0;
+        i_mem_wreg = 5'd0;
+        i_mem_result = 32'd0;
+        i_reset = 1'b1;
+        repeat (2) @(posedge i_clk);
+        i_reset = 1'b0;
+        for (i = 0; i < 12; i = i + 1) begin
+            @(negedge i_clk);
+            i_interrupt = $random(seed) & 1'd1;
+            i_halt = $random(seed) & 1'd1;
+            i_clear_cache = $random(seed) & 1'd1;
+            i_dbg_wreg = $random(seed) & 5'd31;
+            i_dbg_we = $random(seed) & 1'd1;
+            i_dbg_data = $random(seed) & 32'd4294967295;
+            i_dbg_rreg = $random(seed) & 5'd31;
+            i_pf_valid = $random(seed) & 1'd1;
+            i_pf_illegal = $random(seed) & 1'd1;
+            i_pf_instruction = $random(seed) & 32'd4294967295;
+            i_pf_instruction_pc = $random(seed) & 1'd1;
+            i_mem_busy = $random(seed) & 1'd1;
+            i_mem_rdbusy = $random(seed) & 1'd1;
+            i_mem_pipe_stalled = $random(seed) & 1'd1;
+            i_mem_valid = $random(seed) & 1'd1;
+            i_bus_err = $random(seed) & 1'd1;
+            i_mem_wreg = $random(seed) & 5'd31;
+            i_mem_result = $random(seed) & 32'd4294967295;
+            @(posedge i_clk);
+        end
+        #1;
+        $finish;
+    end
+endmodule