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ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
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examples/github_cpu_validation/results/github_cpu_validation_summary.json Normal file
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{
"timestamp_utc": "2026-04-19T06:38:06.434830+00:00",
"repo_root": "/Users/ningyedong/Coding/Verilog-Learn",
"workspace": "/private/tmp/chipverify_github_cpu_example",
"projects_file": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/projects.json",
"tool": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py",
"results": [
{
"name": "ultraembedded_riscv_core",
"repo": "https://github.com/ultraembedded/riscv.git",
"stars": 1703,
"status": "pass",
"clone_status": "updated",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv",
"top": "riscv_core",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v",
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"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/run.log"
}
},
{
"name": "zipcpu",
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"stars": 1535,
"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl",
"top": "zipcore",
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"artifacts": {
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"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log",
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},
{
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"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl",
"top": "e203_cpu_top",
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"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/run.log"
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"total": 3
}