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ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl --top e203_cpu_top --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl --cycles 8 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 136 Verilog files
Selected top module: e203_cpu_top
Top module file: /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl/e203/core/e203_cpu_top.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
STDERR:

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VCD info: dumpfile e203_cpu_top_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v:232: $finish called at 96000 (1ps)

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`timescale 1ns/1ps
module tb_e203_cpu_top_auto;
reg pc_rtvec;
reg dcsr_r;
reg dpc_r;
reg dscratch_r;
reg dbg_mode;
reg dbg_halt_r;
reg dbg_step_r;
reg dbg_ebreakm_r;
reg dbg_stopcycle;
reg dbg_irq_a;
reg core_mhartid;
reg ext_irq_a;
reg sft_irq_a;
reg tmr_irq_a;
reg tcm_sd;
reg tcm_ds;
reg ext2itcm_icb_cmd_valid;
reg ext2itcm_icb_cmd_addr;
reg ext2itcm_icb_cmd_read;
reg ext2itcm_icb_cmd_wdata;
reg ext2itcm_icb_cmd_wmask;
reg ext2itcm_icb_rsp_ready;
reg ext2dtcm_icb_cmd_valid;
reg ext2dtcm_icb_cmd_addr;
reg ext2dtcm_icb_cmd_read;
reg ext2dtcm_icb_cmd_wdata;
reg ext2dtcm_icb_cmd_wmask;
reg ext2dtcm_icb_rsp_ready;
reg ppi_icb_cmd_ready;
reg ppi_icb_rsp_valid;
reg ppi_icb_rsp_err;
reg ppi_icb_rsp_rdata;
reg clint_icb_cmd_ready;
reg clint_icb_rsp_valid;
reg clint_icb_rsp_err;
reg clint_icb_rsp_rdata;
reg plic_icb_cmd_ready;
reg plic_icb_rsp_valid;
reg plic_icb_rsp_err;
reg plic_icb_rsp_rdata;
reg fio_icb_cmd_ready;
reg fio_icb_rsp_valid;
reg fio_icb_rsp_err;
reg fio_icb_rsp_rdata;
reg mem_icb_cmd_ready;
reg mem_icb_rsp_valid;
reg mem_icb_rsp_err;
reg mem_icb_rsp_rdata;
reg test_mode;
reg clk;
reg rst_n;
wire inspect_pc;
wire inspect_dbg_irq;
wire inspect_mem_cmd_valid;
wire inspect_mem_cmd_ready;
wire inspect_mem_rsp_valid;
wire inspect_mem_rsp_ready;
wire inspect_core_clk;
wire core_csr_clk;
wire core_wfi;
wire tm_stop;
wire dbg_irq_r;
wire cmt_dpc;
wire cmt_dpc_ena;
wire cmt_dcause;
wire cmt_dcause_ena;
wire wr_dcsr_ena;
wire wr_dpc_ena;
wire wr_dscratch_ena;
wire wr_csr_nxt;
wire ext2itcm_icb_cmd_ready;
wire ext2itcm_icb_rsp_valid;
wire ext2itcm_icb_rsp_err;
wire ext2itcm_icb_rsp_rdata;
wire ext2dtcm_icb_cmd_ready;
wire ext2dtcm_icb_rsp_valid;
wire ext2dtcm_icb_rsp_err;
wire ext2dtcm_icb_rsp_rdata;
wire ppi_icb_cmd_valid;
wire ppi_icb_cmd_addr;
wire ppi_icb_cmd_read;
wire ppi_icb_cmd_wdata;
wire ppi_icb_cmd_wmask;
wire ppi_icb_rsp_ready;
wire clint_icb_cmd_valid;
wire clint_icb_cmd_addr;
wire clint_icb_cmd_read;
wire clint_icb_cmd_wdata;
wire clint_icb_cmd_wmask;
wire clint_icb_rsp_ready;
wire plic_icb_cmd_valid;
wire plic_icb_cmd_addr;
wire plic_icb_cmd_read;
wire plic_icb_cmd_wdata;
wire plic_icb_cmd_wmask;
wire plic_icb_rsp_ready;
wire fio_icb_cmd_valid;
wire fio_icb_cmd_addr;
wire fio_icb_cmd_read;
wire fio_icb_cmd_wdata;
wire fio_icb_cmd_wmask;
wire fio_icb_rsp_ready;
wire mem_icb_cmd_valid;
wire mem_icb_cmd_addr;
wire mem_icb_cmd_read;
wire mem_icb_cmd_wdata;
wire mem_icb_cmd_wmask;
wire mem_icb_rsp_ready;
integer i;
integer seed;
e203_cpu_top dut (.inspect_pc(inspect_pc), .inspect_dbg_irq(inspect_dbg_irq), .inspect_mem_cmd_valid(inspect_mem_cmd_valid), .inspect_mem_cmd_ready(inspect_mem_cmd_ready), .inspect_mem_rsp_valid(inspect_mem_rsp_valid), .inspect_mem_rsp_ready(inspect_mem_rsp_ready), .inspect_core_clk(inspect_core_clk), .core_csr_clk(core_csr_clk), .core_wfi(core_wfi), .tm_stop(tm_stop), .pc_rtvec(pc_rtvec), .dbg_irq_r(dbg_irq_r), .cmt_dpc(cmt_dpc), .cmt_dpc_ena(cmt_dpc_ena), .cmt_dcause(cmt_dcause), .cmt_dcause_ena(cmt_dcause_ena), .wr_dcsr_ena(wr_dcsr_ena), .wr_dpc_ena(wr_dpc_ena), .wr_dscratch_ena(wr_dscratch_ena), .wr_csr_nxt(wr_csr_nxt), .dcsr_r(dcsr_r), .dpc_r(dpc_r), .dscratch_r(dscratch_r), .dbg_mode(dbg_mode), .dbg_halt_r(dbg_halt_r), .dbg_step_r(dbg_step_r), .dbg_ebreakm_r(dbg_ebreakm_r), .dbg_stopcycle(dbg_stopcycle), .dbg_irq_a(dbg_irq_a), .core_mhartid(core_mhartid), .ext_irq_a(ext_irq_a), .sft_irq_a(sft_irq_a), .tmr_irq_a(tmr_irq_a), .tcm_sd(tcm_sd), .tcm_ds(tcm_ds), .ext2itcm_icb_cmd_valid(ext2itcm_icb_cmd_valid), .ext2itcm_icb_cmd_ready(ext2itcm_icb_cmd_ready), .ext2itcm_icb_cmd_addr(ext2itcm_icb_cmd_addr), .ext2itcm_icb_cmd_read(ext2itcm_icb_cmd_read), .ext2itcm_icb_cmd_wdata(ext2itcm_icb_cmd_wdata), .ext2itcm_icb_cmd_wmask(ext2itcm_icb_cmd_wmask), .ext2itcm_icb_rsp_valid(ext2itcm_icb_rsp_valid), .ext2itcm_icb_rsp_ready(ext2itcm_icb_rsp_ready), .ext2itcm_icb_rsp_err(ext2itcm_icb_rsp_err), .ext2itcm_icb_rsp_rdata(ext2itcm_icb_rsp_rdata), .ext2dtcm_icb_cmd_valid(ext2dtcm_icb_cmd_valid), .ext2dtcm_icb_cmd_ready(ext2dtcm_icb_cmd_ready), .ext2dtcm_icb_cmd_addr(ext2dtcm_icb_cmd_addr), .ext2dtcm_icb_cmd_read(ext2dtcm_icb_cmd_read), .ext2dtcm_icb_cmd_wdata(ext2dtcm_icb_cmd_wdata), .ext2dtcm_icb_cmd_wmask(ext2dtcm_icb_cmd_wmask), .ext2dtcm_icb_rsp_valid(ext2dtcm_icb_rsp_valid), .ext2dtcm_icb_rsp_ready(ext2dtcm_icb_rsp_ready), .ext2dtcm_icb_rsp_err(ext2dtcm_icb_rsp_err), .ext2dtcm_icb_rsp_rdata(ext2dtcm_icb_rsp_rdata), .ppi_icb_cmd_valid(ppi_icb_cmd_valid), .ppi_icb_cmd_ready(ppi_icb_cmd_ready), .ppi_icb_cmd_addr(ppi_icb_cmd_addr), .ppi_icb_cmd_read(ppi_icb_cmd_read), .ppi_icb_cmd_wdata(ppi_icb_cmd_wdata), .ppi_icb_cmd_wmask(ppi_icb_cmd_wmask), .ppi_icb_rsp_valid(ppi_icb_rsp_valid), .ppi_icb_rsp_ready(ppi_icb_rsp_ready), .ppi_icb_rsp_err(ppi_icb_rsp_err), .ppi_icb_rsp_rdata(ppi_icb_rsp_rdata), .clint_icb_cmd_valid(clint_icb_cmd_valid), .clint_icb_cmd_ready(clint_icb_cmd_ready), .clint_icb_cmd_addr(clint_icb_cmd_addr), .clint_icb_cmd_read(clint_icb_cmd_read), .clint_icb_cmd_wdata(clint_icb_cmd_wdata), .clint_icb_cmd_wmask(clint_icb_cmd_wmask), .clint_icb_rsp_valid(clint_icb_rsp_valid), .clint_icb_rsp_ready(clint_icb_rsp_ready), .clint_icb_rsp_err(clint_icb_rsp_err), .clint_icb_rsp_rdata(clint_icb_rsp_rdata), .plic_icb_cmd_valid(plic_icb_cmd_valid), .plic_icb_cmd_ready(plic_icb_cmd_ready), .plic_icb_cmd_addr(plic_icb_cmd_addr), .plic_icb_cmd_read(plic_icb_cmd_read), .plic_icb_cmd_wdata(plic_icb_cmd_wdata), .plic_icb_cmd_wmask(plic_icb_cmd_wmask), .plic_icb_rsp_valid(plic_icb_rsp_valid), .plic_icb_rsp_ready(plic_icb_rsp_ready), .plic_icb_rsp_err(plic_icb_rsp_err), .plic_icb_rsp_rdata(plic_icb_rsp_rdata), .fio_icb_cmd_valid(fio_icb_cmd_valid), .fio_icb_cmd_ready(fio_icb_cmd_ready), .fio_icb_cmd_addr(fio_icb_cmd_addr), .fio_icb_cmd_read(fio_icb_cmd_read), .fio_icb_cmd_wdata(fio_icb_cmd_wdata), .fio_icb_cmd_wmask(fio_icb_cmd_wmask), .fio_icb_rsp_valid(fio_icb_rsp_valid), .fio_icb_rsp_ready(fio_icb_rsp_ready), .fio_icb_rsp_err(fio_icb_rsp_err), .fio_icb_rsp_rdata(fio_icb_rsp_rdata), .mem_icb_cmd_valid(mem_icb_cmd_valid), .mem_icb_cmd_ready(mem_icb_cmd_ready), .mem_icb_cmd_addr(mem_icb_cmd_addr), .mem_icb_cmd_read(mem_icb_cmd_read), .mem_icb_cmd_wdata(mem_icb_cmd_wdata), .mem_icb_cmd_wmask(mem_icb_cmd_wmask), .mem_icb_rsp_valid(mem_icb_rsp_valid), .mem_icb_rsp_ready(mem_icb_rsp_ready), .mem_icb_rsp_err(mem_icb_rsp_err), .mem_icb_rsp_rdata(mem_icb_rsp_rdata), .test_mode(test_mode), .clk(clk), .rst_n(rst_n));
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
seed = 20260419;
$dumpfile("e203_cpu_top_auto.vcd");
$dumpvars(0, tb_e203_cpu_top_auto);
pc_rtvec = 1'd0;
dcsr_r = 1'd0;
dpc_r = 1'd0;
dscratch_r = 1'd0;
dbg_mode = 1'd0;
dbg_halt_r = 1'd0;
dbg_step_r = 1'd0;
dbg_ebreakm_r = 1'd0;
dbg_stopcycle = 1'd0;
dbg_irq_a = 1'd0;
core_mhartid = 1'd0;
ext_irq_a = 1'd0;
sft_irq_a = 1'd0;
tmr_irq_a = 1'd0;
tcm_sd = 1'd0;
tcm_ds = 1'd0;
ext2itcm_icb_cmd_valid = 1'd0;
ext2itcm_icb_cmd_addr = 1'd0;
ext2itcm_icb_cmd_read = 1'd0;
ext2itcm_icb_cmd_wdata = 1'd0;
ext2itcm_icb_cmd_wmask = 1'd0;
ext2itcm_icb_rsp_ready = 1'd0;
ext2dtcm_icb_cmd_valid = 1'd0;
ext2dtcm_icb_cmd_addr = 1'd0;
ext2dtcm_icb_cmd_read = 1'd0;
ext2dtcm_icb_cmd_wdata = 1'd0;
ext2dtcm_icb_cmd_wmask = 1'd0;
ext2dtcm_icb_rsp_ready = 1'd0;
ppi_icb_cmd_ready = 1'd0;
ppi_icb_rsp_valid = 1'd0;
ppi_icb_rsp_err = 1'd0;
ppi_icb_rsp_rdata = 1'd0;
clint_icb_cmd_ready = 1'd0;
clint_icb_rsp_valid = 1'd0;
clint_icb_rsp_err = 1'd0;
clint_icb_rsp_rdata = 1'd0;
plic_icb_cmd_ready = 1'd0;
plic_icb_rsp_valid = 1'd0;
plic_icb_rsp_err = 1'd0;
plic_icb_rsp_rdata = 1'd0;
fio_icb_cmd_ready = 1'd0;
fio_icb_rsp_valid = 1'd0;
fio_icb_rsp_err = 1'd0;
fio_icb_rsp_rdata = 1'd0;
mem_icb_cmd_ready = 1'd0;
mem_icb_rsp_valid = 1'd0;
mem_icb_rsp_err = 1'd0;
mem_icb_rsp_rdata = 1'd0;
test_mode = 1'd0;
rst_n = 1'b0;
repeat (2) @(posedge clk);
rst_n = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
@(negedge clk);
pc_rtvec = $random(seed) & 1'd1;
dcsr_r = $random(seed) & 1'd1;
dpc_r = $random(seed) & 1'd1;
dscratch_r = $random(seed) & 1'd1;
dbg_mode = $random(seed) & 1'd1;
dbg_halt_r = $random(seed) & 1'd1;
dbg_step_r = $random(seed) & 1'd1;
dbg_ebreakm_r = $random(seed) & 1'd1;
dbg_stopcycle = $random(seed) & 1'd1;
dbg_irq_a = $random(seed) & 1'd1;
core_mhartid = $random(seed) & 1'd1;
ext_irq_a = $random(seed) & 1'd1;
sft_irq_a = $random(seed) & 1'd1;
tmr_irq_a = $random(seed) & 1'd1;
tcm_sd = $random(seed) & 1'd1;
tcm_ds = $random(seed) & 1'd1;
ext2itcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2itcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2itcm_icb_cmd_read = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2itcm_icb_rsp_ready = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_read = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2dtcm_icb_rsp_ready = $random(seed) & 1'd1;
ppi_icb_cmd_ready = $random(seed) & 1'd1;
ppi_icb_rsp_valid = $random(seed) & 1'd1;
ppi_icb_rsp_err = $random(seed) & 1'd1;
ppi_icb_rsp_rdata = $random(seed) & 1'd1;
clint_icb_cmd_ready = $random(seed) & 1'd1;
clint_icb_rsp_valid = $random(seed) & 1'd1;
clint_icb_rsp_err = $random(seed) & 1'd1;
clint_icb_rsp_rdata = $random(seed) & 1'd1;
plic_icb_cmd_ready = $random(seed) & 1'd1;
plic_icb_rsp_valid = $random(seed) & 1'd1;
plic_icb_rsp_err = $random(seed) & 1'd1;
plic_icb_rsp_rdata = $random(seed) & 1'd1;
fio_icb_cmd_ready = $random(seed) & 1'd1;
fio_icb_rsp_valid = $random(seed) & 1'd1;
fio_icb_rsp_err = $random(seed) & 1'd1;
fio_icb_rsp_rdata = $random(seed) & 1'd1;
mem_icb_cmd_ready = $random(seed) & 1'd1;
mem_icb_rsp_valid = $random(seed) & 1'd1;
mem_icb_rsp_err = $random(seed) & 1'd1;
mem_icb_rsp_rdata = $random(seed) & 1'd1;
test_mode = $random(seed) & 1'd1;
@(posedge clk);
end
#1;
$finish;
end
endmodule