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ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
54 changed files with 80296 additions and 0 deletions
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examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out Normal file
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examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd Normal file
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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl --top e203_cpu_top --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl --cycles 8 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 136 Verilog files
Selected top module: e203_cpu_top
Top module file: /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl/e203/core/e203_cpu_top.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
STDERR:

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examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log Normal file
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VCD info: dumpfile e203_cpu_top_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v:232: $finish called at 96000 (1ps)

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examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v Normal file
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`timescale 1ns/1ps
module tb_e203_cpu_top_auto;
reg pc_rtvec;
reg dcsr_r;
reg dpc_r;
reg dscratch_r;
reg dbg_mode;
reg dbg_halt_r;
reg dbg_step_r;
reg dbg_ebreakm_r;
reg dbg_stopcycle;
reg dbg_irq_a;
reg core_mhartid;
reg ext_irq_a;
reg sft_irq_a;
reg tmr_irq_a;
reg tcm_sd;
reg tcm_ds;
reg ext2itcm_icb_cmd_valid;
reg ext2itcm_icb_cmd_addr;
reg ext2itcm_icb_cmd_read;
reg ext2itcm_icb_cmd_wdata;
reg ext2itcm_icb_cmd_wmask;
reg ext2itcm_icb_rsp_ready;
reg ext2dtcm_icb_cmd_valid;
reg ext2dtcm_icb_cmd_addr;
reg ext2dtcm_icb_cmd_read;
reg ext2dtcm_icb_cmd_wdata;
reg ext2dtcm_icb_cmd_wmask;
reg ext2dtcm_icb_rsp_ready;
reg ppi_icb_cmd_ready;
reg ppi_icb_rsp_valid;
reg ppi_icb_rsp_err;
reg ppi_icb_rsp_rdata;
reg clint_icb_cmd_ready;
reg clint_icb_rsp_valid;
reg clint_icb_rsp_err;
reg clint_icb_rsp_rdata;
reg plic_icb_cmd_ready;
reg plic_icb_rsp_valid;
reg plic_icb_rsp_err;
reg plic_icb_rsp_rdata;
reg fio_icb_cmd_ready;
reg fio_icb_rsp_valid;
reg fio_icb_rsp_err;
reg fio_icb_rsp_rdata;
reg mem_icb_cmd_ready;
reg mem_icb_rsp_valid;
reg mem_icb_rsp_err;
reg mem_icb_rsp_rdata;
reg test_mode;
reg clk;
reg rst_n;
wire inspect_pc;
wire inspect_dbg_irq;
wire inspect_mem_cmd_valid;
wire inspect_mem_cmd_ready;
wire inspect_mem_rsp_valid;
wire inspect_mem_rsp_ready;
wire inspect_core_clk;
wire core_csr_clk;
wire core_wfi;
wire tm_stop;
wire dbg_irq_r;
wire cmt_dpc;
wire cmt_dpc_ena;
wire cmt_dcause;
wire cmt_dcause_ena;
wire wr_dcsr_ena;
wire wr_dpc_ena;
wire wr_dscratch_ena;
wire wr_csr_nxt;
wire ext2itcm_icb_cmd_ready;
wire ext2itcm_icb_rsp_valid;
wire ext2itcm_icb_rsp_err;
wire ext2itcm_icb_rsp_rdata;
wire ext2dtcm_icb_cmd_ready;
wire ext2dtcm_icb_rsp_valid;
wire ext2dtcm_icb_rsp_err;
wire ext2dtcm_icb_rsp_rdata;
wire ppi_icb_cmd_valid;
wire ppi_icb_cmd_addr;
wire ppi_icb_cmd_read;
wire ppi_icb_cmd_wdata;
wire ppi_icb_cmd_wmask;
wire ppi_icb_rsp_ready;
wire clint_icb_cmd_valid;
wire clint_icb_cmd_addr;
wire clint_icb_cmd_read;
wire clint_icb_cmd_wdata;
wire clint_icb_cmd_wmask;
wire clint_icb_rsp_ready;
wire plic_icb_cmd_valid;
wire plic_icb_cmd_addr;
wire plic_icb_cmd_read;
wire plic_icb_cmd_wdata;
wire plic_icb_cmd_wmask;
wire plic_icb_rsp_ready;
wire fio_icb_cmd_valid;
wire fio_icb_cmd_addr;
wire fio_icb_cmd_read;
wire fio_icb_cmd_wdata;
wire fio_icb_cmd_wmask;
wire fio_icb_rsp_ready;
wire mem_icb_cmd_valid;
wire mem_icb_cmd_addr;
wire mem_icb_cmd_read;
wire mem_icb_cmd_wdata;
wire mem_icb_cmd_wmask;
wire mem_icb_rsp_ready;
integer i;
integer seed;
e203_cpu_top dut (.inspect_pc(inspect_pc), .inspect_dbg_irq(inspect_dbg_irq), .inspect_mem_cmd_valid(inspect_mem_cmd_valid), .inspect_mem_cmd_ready(inspect_mem_cmd_ready), .inspect_mem_rsp_valid(inspect_mem_rsp_valid), .inspect_mem_rsp_ready(inspect_mem_rsp_ready), .inspect_core_clk(inspect_core_clk), .core_csr_clk(core_csr_clk), .core_wfi(core_wfi), .tm_stop(tm_stop), .pc_rtvec(pc_rtvec), .dbg_irq_r(dbg_irq_r), .cmt_dpc(cmt_dpc), .cmt_dpc_ena(cmt_dpc_ena), .cmt_dcause(cmt_dcause), .cmt_dcause_ena(cmt_dcause_ena), .wr_dcsr_ena(wr_dcsr_ena), .wr_dpc_ena(wr_dpc_ena), .wr_dscratch_ena(wr_dscratch_ena), .wr_csr_nxt(wr_csr_nxt), .dcsr_r(dcsr_r), .dpc_r(dpc_r), .dscratch_r(dscratch_r), .dbg_mode(dbg_mode), .dbg_halt_r(dbg_halt_r), .dbg_step_r(dbg_step_r), .dbg_ebreakm_r(dbg_ebreakm_r), .dbg_stopcycle(dbg_stopcycle), .dbg_irq_a(dbg_irq_a), .core_mhartid(core_mhartid), .ext_irq_a(ext_irq_a), .sft_irq_a(sft_irq_a), .tmr_irq_a(tmr_irq_a), .tcm_sd(tcm_sd), .tcm_ds(tcm_ds), .ext2itcm_icb_cmd_valid(ext2itcm_icb_cmd_valid), .ext2itcm_icb_cmd_ready(ext2itcm_icb_cmd_ready), .ext2itcm_icb_cmd_addr(ext2itcm_icb_cmd_addr), .ext2itcm_icb_cmd_read(ext2itcm_icb_cmd_read), .ext2itcm_icb_cmd_wdata(ext2itcm_icb_cmd_wdata), .ext2itcm_icb_cmd_wmask(ext2itcm_icb_cmd_wmask), .ext2itcm_icb_rsp_valid(ext2itcm_icb_rsp_valid), .ext2itcm_icb_rsp_ready(ext2itcm_icb_rsp_ready), .ext2itcm_icb_rsp_err(ext2itcm_icb_rsp_err), .ext2itcm_icb_rsp_rdata(ext2itcm_icb_rsp_rdata), .ext2dtcm_icb_cmd_valid(ext2dtcm_icb_cmd_valid), .ext2dtcm_icb_cmd_ready(ext2dtcm_icb_cmd_ready), .ext2dtcm_icb_cmd_addr(ext2dtcm_icb_cmd_addr), .ext2dtcm_icb_cmd_read(ext2dtcm_icb_cmd_read), .ext2dtcm_icb_cmd_wdata(ext2dtcm_icb_cmd_wdata), .ext2dtcm_icb_cmd_wmask(ext2dtcm_icb_cmd_wmask), .ext2dtcm_icb_rsp_valid(ext2dtcm_icb_rsp_valid), .ext2dtcm_icb_rsp_ready(ext2dtcm_icb_rsp_ready), .ext2dtcm_icb_rsp_err(ext2dtcm_icb_rsp_err), .ext2dtcm_icb_rsp_rdata(ext2dtcm_icb_rsp_rdata), .ppi_icb_cmd_valid(ppi_icb_cmd_valid), .ppi_icb_cmd_ready(ppi_icb_cmd_ready), .ppi_icb_cmd_addr(ppi_icb_cmd_addr), .ppi_icb_cmd_read(ppi_icb_cmd_read), .ppi_icb_cmd_wdata(ppi_icb_cmd_wdata), .ppi_icb_cmd_wmask(ppi_icb_cmd_wmask), .ppi_icb_rsp_valid(ppi_icb_rsp_valid), .ppi_icb_rsp_ready(ppi_icb_rsp_ready), .ppi_icb_rsp_err(ppi_icb_rsp_err), .ppi_icb_rsp_rdata(ppi_icb_rsp_rdata), .clint_icb_cmd_valid(clint_icb_cmd_valid), .clint_icb_cmd_ready(clint_icb_cmd_ready), .clint_icb_cmd_addr(clint_icb_cmd_addr), .clint_icb_cmd_read(clint_icb_cmd_read), .clint_icb_cmd_wdata(clint_icb_cmd_wdata), .clint_icb_cmd_wmask(clint_icb_cmd_wmask), .clint_icb_rsp_valid(clint_icb_rsp_valid), .clint_icb_rsp_ready(clint_icb_rsp_ready), .clint_icb_rsp_err(clint_icb_rsp_err), .clint_icb_rsp_rdata(clint_icb_rsp_rdata), .plic_icb_cmd_valid(plic_icb_cmd_valid), .plic_icb_cmd_ready(plic_icb_cmd_ready), .plic_icb_cmd_addr(plic_icb_cmd_addr), .plic_icb_cmd_read(plic_icb_cmd_read), .plic_icb_cmd_wdata(plic_icb_cmd_wdata), .plic_icb_cmd_wmask(plic_icb_cmd_wmask), .plic_icb_rsp_valid(plic_icb_rsp_valid), .plic_icb_rsp_ready(plic_icb_rsp_ready), .plic_icb_rsp_err(plic_icb_rsp_err), .plic_icb_rsp_rdata(plic_icb_rsp_rdata), .fio_icb_cmd_valid(fio_icb_cmd_valid), .fio_icb_cmd_ready(fio_icb_cmd_ready), .fio_icb_cmd_addr(fio_icb_cmd_addr), .fio_icb_cmd_read(fio_icb_cmd_read), .fio_icb_cmd_wdata(fio_icb_cmd_wdata), .fio_icb_cmd_wmask(fio_icb_cmd_wmask), .fio_icb_rsp_valid(fio_icb_rsp_valid), .fio_icb_rsp_ready(fio_icb_rsp_ready), .fio_icb_rsp_err(fio_icb_rsp_err), .fio_icb_rsp_rdata(fio_icb_rsp_rdata), .mem_icb_cmd_valid(mem_icb_cmd_valid), .mem_icb_cmd_ready(mem_icb_cmd_ready), .mem_icb_cmd_addr(mem_icb_cmd_addr), .mem_icb_cmd_read(mem_icb_cmd_read), .mem_icb_cmd_wdata(mem_icb_cmd_wdata), .mem_icb_cmd_wmask(mem_icb_cmd_wmask), .mem_icb_rsp_valid(mem_icb_rsp_valid), .mem_icb_rsp_ready(mem_icb_rsp_ready), .mem_icb_rsp_err(mem_icb_rsp_err), .mem_icb_rsp_rdata(mem_icb_rsp_rdata), .test_mode(test_mode), .clk(clk), .rst_n(rst_n));
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
seed = 20260419;
$dumpfile("e203_cpu_top_auto.vcd");
$dumpvars(0, tb_e203_cpu_top_auto);
pc_rtvec = 1'd0;
dcsr_r = 1'd0;
dpc_r = 1'd0;
dscratch_r = 1'd0;
dbg_mode = 1'd0;
dbg_halt_r = 1'd0;
dbg_step_r = 1'd0;
dbg_ebreakm_r = 1'd0;
dbg_stopcycle = 1'd0;
dbg_irq_a = 1'd0;
core_mhartid = 1'd0;
ext_irq_a = 1'd0;
sft_irq_a = 1'd0;
tmr_irq_a = 1'd0;
tcm_sd = 1'd0;
tcm_ds = 1'd0;
ext2itcm_icb_cmd_valid = 1'd0;
ext2itcm_icb_cmd_addr = 1'd0;
ext2itcm_icb_cmd_read = 1'd0;
ext2itcm_icb_cmd_wdata = 1'd0;
ext2itcm_icb_cmd_wmask = 1'd0;
ext2itcm_icb_rsp_ready = 1'd0;
ext2dtcm_icb_cmd_valid = 1'd0;
ext2dtcm_icb_cmd_addr = 1'd0;
ext2dtcm_icb_cmd_read = 1'd0;
ext2dtcm_icb_cmd_wdata = 1'd0;
ext2dtcm_icb_cmd_wmask = 1'd0;
ext2dtcm_icb_rsp_ready = 1'd0;
ppi_icb_cmd_ready = 1'd0;
ppi_icb_rsp_valid = 1'd0;
ppi_icb_rsp_err = 1'd0;
ppi_icb_rsp_rdata = 1'd0;
clint_icb_cmd_ready = 1'd0;
clint_icb_rsp_valid = 1'd0;
clint_icb_rsp_err = 1'd0;
clint_icb_rsp_rdata = 1'd0;
plic_icb_cmd_ready = 1'd0;
plic_icb_rsp_valid = 1'd0;
plic_icb_rsp_err = 1'd0;
plic_icb_rsp_rdata = 1'd0;
fio_icb_cmd_ready = 1'd0;
fio_icb_rsp_valid = 1'd0;
fio_icb_rsp_err = 1'd0;
fio_icb_rsp_rdata = 1'd0;
mem_icb_cmd_ready = 1'd0;
mem_icb_rsp_valid = 1'd0;
mem_icb_rsp_err = 1'd0;
mem_icb_rsp_rdata = 1'd0;
test_mode = 1'd0;
rst_n = 1'b0;
repeat (2) @(posedge clk);
rst_n = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
@(negedge clk);
pc_rtvec = $random(seed) & 1'd1;
dcsr_r = $random(seed) & 1'd1;
dpc_r = $random(seed) & 1'd1;
dscratch_r = $random(seed) & 1'd1;
dbg_mode = $random(seed) & 1'd1;
dbg_halt_r = $random(seed) & 1'd1;
dbg_step_r = $random(seed) & 1'd1;
dbg_ebreakm_r = $random(seed) & 1'd1;
dbg_stopcycle = $random(seed) & 1'd1;
dbg_irq_a = $random(seed) & 1'd1;
core_mhartid = $random(seed) & 1'd1;
ext_irq_a = $random(seed) & 1'd1;
sft_irq_a = $random(seed) & 1'd1;
tmr_irq_a = $random(seed) & 1'd1;
tcm_sd = $random(seed) & 1'd1;
tcm_ds = $random(seed) & 1'd1;
ext2itcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2itcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2itcm_icb_cmd_read = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2itcm_icb_rsp_ready = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_read = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2dtcm_icb_rsp_ready = $random(seed) & 1'd1;
ppi_icb_cmd_ready = $random(seed) & 1'd1;
ppi_icb_rsp_valid = $random(seed) & 1'd1;
ppi_icb_rsp_err = $random(seed) & 1'd1;
ppi_icb_rsp_rdata = $random(seed) & 1'd1;
clint_icb_cmd_ready = $random(seed) & 1'd1;
clint_icb_rsp_valid = $random(seed) & 1'd1;
clint_icb_rsp_err = $random(seed) & 1'd1;
clint_icb_rsp_rdata = $random(seed) & 1'd1;
plic_icb_cmd_ready = $random(seed) & 1'd1;
plic_icb_rsp_valid = $random(seed) & 1'd1;
plic_icb_rsp_err = $random(seed) & 1'd1;
plic_icb_rsp_rdata = $random(seed) & 1'd1;
fio_icb_cmd_ready = $random(seed) & 1'd1;
fio_icb_rsp_valid = $random(seed) & 1'd1;
fio_icb_rsp_err = $random(seed) & 1'd1;
fio_icb_rsp_rdata = $random(seed) & 1'd1;
mem_icb_cmd_ready = $random(seed) & 1'd1;
mem_icb_rsp_valid = $random(seed) & 1'd1;
mem_icb_rsp_err = $random(seed) & 1'd1;
mem_icb_rsp_rdata = $random(seed) & 1'd1;
test_mode = $random(seed) & 1'd1;
@(posedge clk);
end
#1;
$finish;
end
endmodule

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{
"timestamp_utc": "2026-04-19T06:38:06.434830+00:00",
"repo_root": "/Users/ningyedong/Coding/Verilog-Learn",
"workspace": "/private/tmp/chipverify_github_cpu_example",
"projects_file": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/projects.json",
"tool": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py",
"results": [
{
"name": "ultraembedded_riscv_core",
"repo": "https://github.com/ultraembedded/riscv.git",
"stars": 1703,
"status": "pass",
"clone_status": "updated",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv",
"top": "riscv_core",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/run.log"
}
},
{
"name": "zipcpu",
"repo": "https://github.com/ZipCPU/zipcpu.git",
"stars": 1535,
"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl",
"top": "zipcore",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/run.log"
}
},
{
"name": "e203_cpu_top_fullrtl",
"repo": "https://github.com/riscv-mcu/e203_hbirdv2.git",
"stars": 1811,
"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl",
"top": "e203_cpu_top",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/run.log"
}
}
],
"pass_count": 3,
"fail_count": 0,
"total": 3
}

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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv --top riscv_core --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core --cycles 12 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 18 Verilog files
Selected top module: riscv_core
Top module file: /private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv/riscv_core.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd
STDERR:

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VCD info: dumpfile riscv_core_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v:71: $finish called at 12000 (1ps)

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`timescale 1ns/1ps
module tb_riscv_core_auto;
reg clk_i;
reg rst_i;
reg [31:0] mem_d_data_rd_i;
reg mem_d_accept_i;
reg mem_d_ack_i;
reg mem_d_error_i;
reg [10:0] mem_d_resp_tag_i;
reg mem_i_accept_i;
reg mem_i_valid_i;
reg mem_i_error_i;
reg [31:0] mem_i_inst_i;
reg intr_i;
reg [31:0] reset_vector_i;
reg [31:0] cpu_id_i;
wire [31:0] mem_d_addr_o;
wire [31:0] mem_d_data_wr_o;
wire mem_d_rd_o;
wire [3:0] mem_d_wr_o;
wire mem_d_cacheable_o;
wire [10:0] mem_d_req_tag_o;
wire mem_d_invalidate_o;
wire mem_d_writeback_o;
wire mem_d_flush_o;
wire mem_i_rd_o;
wire mem_i_flush_o;
wire mem_i_invalidate_o;
wire [31:0] mem_i_pc_o;
integer i;
integer seed;
integer vec;
riscv_core dut (.clk_i(clk_i), .rst_i(rst_i), .mem_d_data_rd_i(mem_d_data_rd_i), .mem_d_accept_i(mem_d_accept_i), .mem_d_ack_i(mem_d_ack_i), .mem_d_error_i(mem_d_error_i), .mem_d_resp_tag_i(mem_d_resp_tag_i), .mem_i_accept_i(mem_i_accept_i), .mem_i_valid_i(mem_i_valid_i), .mem_i_error_i(mem_i_error_i), .mem_i_inst_i(mem_i_inst_i), .intr_i(intr_i), .reset_vector_i(reset_vector_i), .cpu_id_i(cpu_id_i), .mem_d_addr_o(mem_d_addr_o), .mem_d_data_wr_o(mem_d_data_wr_o), .mem_d_rd_o(mem_d_rd_o), .mem_d_wr_o(mem_d_wr_o), .mem_d_cacheable_o(mem_d_cacheable_o), .mem_d_req_tag_o(mem_d_req_tag_o), .mem_d_invalidate_o(mem_d_invalidate_o), .mem_d_writeback_o(mem_d_writeback_o), .mem_d_flush_o(mem_d_flush_o), .mem_i_rd_o(mem_i_rd_o), .mem_i_flush_o(mem_i_flush_o), .mem_i_invalidate_o(mem_i_invalidate_o), .mem_i_pc_o(mem_i_pc_o));
initial begin
seed = 20260419;
$dumpfile("riscv_core_auto.vcd");
$dumpvars(0, tb_riscv_core_auto);
clk_i = 1'd0;
mem_d_data_rd_i = 32'd0;
mem_d_accept_i = 1'd0;
mem_d_ack_i = 1'd0;
mem_d_error_i = 1'd0;
mem_d_resp_tag_i = 11'd0;
mem_i_accept_i = 1'd0;
mem_i_valid_i = 1'd0;
mem_i_error_i = 1'd0;
mem_i_inst_i = 32'd0;
intr_i = 1'd0;
reset_vector_i = 32'd0;
cpu_id_i = 32'd0;
rst_i = 1'b1;
for (i = 0; i < 12; i = i + 1) begin
clk_i = $random(seed) & 1'd1;
mem_d_data_rd_i = $random(seed) & 32'd4294967295;
mem_d_accept_i = $random(seed) & 1'd1;
mem_d_ack_i = $random(seed) & 1'd1;
mem_d_error_i = $random(seed) & 1'd1;
mem_d_resp_tag_i = $random(seed) & 11'd2047;
mem_i_accept_i = $random(seed) & 1'd1;
mem_i_valid_i = $random(seed) & 1'd1;
mem_i_error_i = $random(seed) & 1'd1;
mem_i_inst_i = $random(seed) & 32'd4294967295;
intr_i = $random(seed) & 1'd1;
reset_vector_i = $random(seed) & 32'd4294967295;
cpu_id_i = $random(seed) & 32'd4294967295;
#1;
end
$finish;
end
endmodule

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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl --top zipcore --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu --cycles 12 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 51 Verilog files
Selected top module: zipcore
Top module file: /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl/core/zipcore.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
STDERR:

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VCD info: dumpfile zipcore_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v:106: $finish called at 136000 (1ps)

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`timescale 1ns/1ps
module tb_zipcore_auto;
reg i_clk;
reg i_reset;
reg i_interrupt;
reg i_halt;
reg i_clear_cache;
reg [4:0] i_dbg_wreg;
reg i_dbg_we;
reg [31:0] i_dbg_data;
reg [4:0] i_dbg_rreg;
reg i_pf_valid;
reg i_pf_illegal;
reg [31:0] i_pf_instruction;
reg i_pf_instruction_pc;
reg i_mem_busy;
reg i_mem_rdbusy;
reg i_mem_pipe_stalled;
reg i_mem_valid;
reg i_bus_err;
reg [4:0] i_mem_wreg;
reg [31:0] i_mem_result;
wire o_clken;
wire o_dbg_stall;
wire [31:0] o_dbg_reg;
wire [2:0] o_dbg_cc;
wire o_break;
wire o_pf_new_pc;
wire o_clear_icache;
wire o_pf_ready;
wire o_pf_request_address;
wire o_clear_dcache;
wire o_mem_ce;
wire o_bus_lock;
wire [2:0] o_mem_op;
wire [31:0] o_mem_addr;
wire [31:0] o_mem_data;
wire o_mem_lock_pc;
wire [4:0] o_mem_reg;
wire o_op_stall;
wire o_pf_stall;
wire o_i_count;
wire [31:0] o_debug;
wire o_prof_stb;
wire o_prof_addr;
wire [31:0] o_prof_ticks;
integer i;
integer seed;
zipcore dut (.i_clk(i_clk), .i_reset(i_reset), .i_interrupt(i_interrupt), .o_clken(o_clken), .i_halt(i_halt), .i_clear_cache(i_clear_cache), .i_dbg_wreg(i_dbg_wreg), .i_dbg_we(i_dbg_we), .i_dbg_data(i_dbg_data), .i_dbg_rreg(i_dbg_rreg), .o_dbg_stall(o_dbg_stall), .o_dbg_reg(o_dbg_reg), .o_dbg_cc(o_dbg_cc), .o_break(o_break), .o_pf_new_pc(o_pf_new_pc), .o_clear_icache(o_clear_icache), .o_pf_ready(o_pf_ready), .o_pf_request_address(o_pf_request_address), .i_pf_valid(i_pf_valid), .i_pf_illegal(i_pf_illegal), .i_pf_instruction(i_pf_instruction), .i_pf_instruction_pc(i_pf_instruction_pc), .o_clear_dcache(o_clear_dcache), .o_mem_ce(o_mem_ce), .o_bus_lock(o_bus_lock), .o_mem_op(o_mem_op), .o_mem_addr(o_mem_addr), .o_mem_data(o_mem_data), .o_mem_lock_pc(o_mem_lock_pc), .o_mem_reg(o_mem_reg), .i_mem_busy(i_mem_busy), .i_mem_rdbusy(i_mem_rdbusy), .i_mem_pipe_stalled(i_mem_pipe_stalled), .i_mem_valid(i_mem_valid), .i_bus_err(i_bus_err), .i_mem_wreg(i_mem_wreg), .i_mem_result(i_mem_result), .o_op_stall(o_op_stall), .o_pf_stall(o_pf_stall), .o_i_count(o_i_count), .o_debug(o_debug), .o_prof_stb(o_prof_stb), .o_prof_addr(o_prof_addr), .o_prof_ticks(o_prof_ticks));
initial begin
i_clk = 1'b0;
forever #5 i_clk = ~i_clk;
end
initial begin
seed = 20260419;
$dumpfile("zipcore_auto.vcd");
$dumpvars(0, tb_zipcore_auto);
i_interrupt = 1'd0;
i_halt = 1'd0;
i_clear_cache = 1'd0;
i_dbg_wreg = 5'd0;
i_dbg_we = 1'd0;
i_dbg_data = 32'd0;
i_dbg_rreg = 5'd0;
i_pf_valid = 1'd0;
i_pf_illegal = 1'd0;
i_pf_instruction = 32'd0;
i_pf_instruction_pc = 1'd0;
i_mem_busy = 1'd0;
i_mem_rdbusy = 1'd0;
i_mem_pipe_stalled = 1'd0;
i_mem_valid = 1'd0;
i_bus_err = 1'd0;
i_mem_wreg = 5'd0;
i_mem_result = 32'd0;
i_reset = 1'b1;
repeat (2) @(posedge i_clk);
i_reset = 1'b0;
for (i = 0; i < 12; i = i + 1) begin
@(negedge i_clk);
i_interrupt = $random(seed) & 1'd1;
i_halt = $random(seed) & 1'd1;
i_clear_cache = $random(seed) & 1'd1;
i_dbg_wreg = $random(seed) & 5'd31;
i_dbg_we = $random(seed) & 1'd1;
i_dbg_data = $random(seed) & 32'd4294967295;
i_dbg_rreg = $random(seed) & 5'd31;
i_pf_valid = $random(seed) & 1'd1;
i_pf_illegal = $random(seed) & 1'd1;
i_pf_instruction = $random(seed) & 32'd4294967295;
i_pf_instruction_pc = $random(seed) & 1'd1;
i_mem_busy = $random(seed) & 1'd1;
i_mem_rdbusy = $random(seed) & 1'd1;
i_mem_pipe_stalled = $random(seed) & 1'd1;
i_mem_valid = $random(seed) & 1'd1;
i_bus_err = $random(seed) & 1'd1;
i_mem_wreg = $random(seed) & 5'd31;
i_mem_result = $random(seed) & 32'd4294967295;
@(posedge i_clk);
end
#1;
$finish;
end
endmodule

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