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ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
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examples/and_gate_spec.json Normal file
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{
"kind": "truth_table",
"inputs": [
"a",
"b"
],
"outputs": [
"f"
],
"cases": [
{
"name": "00",
"in": {
"a": 0,
"b": 0
},
"out": {
"f": 0
}
},
{
"name": "01",
"in": {
"a": 0,
"b": 1
},
"out": {
"f": 0
}
},
{
"name": "10",
"in": {
"a": 1,
"b": 0
},
"out": {
"f": 0
}
},
{
"name": "11",
"in": {
"a": 1,
"b": 1
},
"out": {
"f": 1
}
}
]
}

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# GitHub CPU Validation Example (SLWChipVerify)
这个 example 演示如何对热门开源 CPU 项目执行 SLWChipVerify 一键验证流程，并生成可复现结果。
## 已验证项目（按 GitHub Stars）
- `riscv-mcu/e203_hbirdv2`（约 1811 stars）
- 目录：`rtl`
- 顶层：`e203_cpu_top`
- `ultraembedded/riscv`（约 1703 stars）
- 目录：`core/riscv`
- 顶层：`riscv_core`
- `ZipCPU/zipcpu`（约 1535 stars）
- 目录：`rtl`
- 顶层：`zipcore`
> Stars 基于 2026-04-19 采样，后续会变化。
## 前置要求
- Python 3.9+
- `git`
- `iverilog`
- `vvp`
- 可访问 GitHub 网络
## 一键复现
在安装目录执行：
```bash
python3 slwchipverify/examples/github_cpu_validation/run_github_cpu_validation.py
```
运行后会：
- 自动克隆/更新目标仓库到临时目录
- 对每个项目调用 `slwchipverify/one_click_verify.py`
- 在 `slwchipverify/examples/github_cpu_validation/results/` 下生成：
- 每个项目的 TB / 波形 / 仿真日志 / run.log
- 汇总报告 `github_cpu_validation_summary.json`
## 打包 example
```bash
./slwchipverify/examples/github_cpu_validation/package_example.sh
```
会在 `slwchipverify/examples/github_cpu_validation/dist/` 下生成 zip 包，包含：
- `projects.json`
- `run_github_cpu_validation.py`
- 本说明文档
- `results/` 中的汇总报告与验证产物
## 说明
- 该 example 重点验证工具在真实开源 CPU 仓库上的可用性（冒烟级编译+仿真+波形）。
- 对于特别复杂的 SoC 工程，可能仍需定制宏定义、文件筛选或更细粒度目录选择。

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#!/usr/bin/env bash
set -euo pipefail
# 获取脚本目录并定义输出路径。
SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
DIST_DIR="$SCRIPT_DIR/dist"
STAMP="$(date +%Y%m%d_%H%M%S)"
ARCHIVE="$DIST_DIR/slwchipverify_github_cpu_validation_example_${STAMP}.zip"
# 创建打包输出目录。
mkdir -p "$DIST_DIR"
# 仅按白名单打包关键文件与结果目录，避免把无关文件一起打进去。
(
cd "$SCRIPT_DIR"
zip -r "$ARCHIVE" \
README.md \
projects.json \
run_github_cpu_validation.py \
results \
>/dev/null
)
echo "SLWChipVerify 示例已打包: $ARCHIVE"

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[
{
"name": "ultraembedded_riscv_core",
"repo": "https://github.com/ultraembedded/riscv.git",
"stars": 1703,
"rtl_subdir": "core/riscv",
"top": "riscv_core",
"cycles": 12,
"period": 10,
"reset_cycles": 2
},
{
"name": "zipcpu",
"repo": "https://github.com/ZipCPU/zipcpu.git",
"stars": 1535,
"rtl_subdir": "rtl",
"top": "zipcore",
"cycles": 12,
"period": 10,
"reset_cycles": 2
},
{
"name": "e203_cpu_top_fullrtl",
"repo": "https://github.com/riscv-mcu/e203_hbirdv2.git",
"stars": 1811,
"rtl_subdir": "rtl",
"top": "e203_cpu_top",
"cycles": 8,
"period": 10,
"reset_cycles": 2
}
]

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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl --top e203_cpu_top --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl --cycles 8 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 136 Verilog files
Selected top module: e203_cpu_top
Top module file: /private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl/e203/core/e203_cpu_top.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd
STDERR:

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VCD info: dumpfile e203_cpu_top_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v:232: $finish called at 96000 (1ps)

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`timescale 1ns/1ps
module tb_e203_cpu_top_auto;
reg pc_rtvec;
reg dcsr_r;
reg dpc_r;
reg dscratch_r;
reg dbg_mode;
reg dbg_halt_r;
reg dbg_step_r;
reg dbg_ebreakm_r;
reg dbg_stopcycle;
reg dbg_irq_a;
reg core_mhartid;
reg ext_irq_a;
reg sft_irq_a;
reg tmr_irq_a;
reg tcm_sd;
reg tcm_ds;
reg ext2itcm_icb_cmd_valid;
reg ext2itcm_icb_cmd_addr;
reg ext2itcm_icb_cmd_read;
reg ext2itcm_icb_cmd_wdata;
reg ext2itcm_icb_cmd_wmask;
reg ext2itcm_icb_rsp_ready;
reg ext2dtcm_icb_cmd_valid;
reg ext2dtcm_icb_cmd_addr;
reg ext2dtcm_icb_cmd_read;
reg ext2dtcm_icb_cmd_wdata;
reg ext2dtcm_icb_cmd_wmask;
reg ext2dtcm_icb_rsp_ready;
reg ppi_icb_cmd_ready;
reg ppi_icb_rsp_valid;
reg ppi_icb_rsp_err;
reg ppi_icb_rsp_rdata;
reg clint_icb_cmd_ready;
reg clint_icb_rsp_valid;
reg clint_icb_rsp_err;
reg clint_icb_rsp_rdata;
reg plic_icb_cmd_ready;
reg plic_icb_rsp_valid;
reg plic_icb_rsp_err;
reg plic_icb_rsp_rdata;
reg fio_icb_cmd_ready;
reg fio_icb_rsp_valid;
reg fio_icb_rsp_err;
reg fio_icb_rsp_rdata;
reg mem_icb_cmd_ready;
reg mem_icb_rsp_valid;
reg mem_icb_rsp_err;
reg mem_icb_rsp_rdata;
reg test_mode;
reg clk;
reg rst_n;
wire inspect_pc;
wire inspect_dbg_irq;
wire inspect_mem_cmd_valid;
wire inspect_mem_cmd_ready;
wire inspect_mem_rsp_valid;
wire inspect_mem_rsp_ready;
wire inspect_core_clk;
wire core_csr_clk;
wire core_wfi;
wire tm_stop;
wire dbg_irq_r;
wire cmt_dpc;
wire cmt_dpc_ena;
wire cmt_dcause;
wire cmt_dcause_ena;
wire wr_dcsr_ena;
wire wr_dpc_ena;
wire wr_dscratch_ena;
wire wr_csr_nxt;
wire ext2itcm_icb_cmd_ready;
wire ext2itcm_icb_rsp_valid;
wire ext2itcm_icb_rsp_err;
wire ext2itcm_icb_rsp_rdata;
wire ext2dtcm_icb_cmd_ready;
wire ext2dtcm_icb_rsp_valid;
wire ext2dtcm_icb_rsp_err;
wire ext2dtcm_icb_rsp_rdata;
wire ppi_icb_cmd_valid;
wire ppi_icb_cmd_addr;
wire ppi_icb_cmd_read;
wire ppi_icb_cmd_wdata;
wire ppi_icb_cmd_wmask;
wire ppi_icb_rsp_ready;
wire clint_icb_cmd_valid;
wire clint_icb_cmd_addr;
wire clint_icb_cmd_read;
wire clint_icb_cmd_wdata;
wire clint_icb_cmd_wmask;
wire clint_icb_rsp_ready;
wire plic_icb_cmd_valid;
wire plic_icb_cmd_addr;
wire plic_icb_cmd_read;
wire plic_icb_cmd_wdata;
wire plic_icb_cmd_wmask;
wire plic_icb_rsp_ready;
wire fio_icb_cmd_valid;
wire fio_icb_cmd_addr;
wire fio_icb_cmd_read;
wire fio_icb_cmd_wdata;
wire fio_icb_cmd_wmask;
wire fio_icb_rsp_ready;
wire mem_icb_cmd_valid;
wire mem_icb_cmd_addr;
wire mem_icb_cmd_read;
wire mem_icb_cmd_wdata;
wire mem_icb_cmd_wmask;
wire mem_icb_rsp_ready;
integer i;
integer seed;
e203_cpu_top dut (.inspect_pc(inspect_pc), .inspect_dbg_irq(inspect_dbg_irq), .inspect_mem_cmd_valid(inspect_mem_cmd_valid), .inspect_mem_cmd_ready(inspect_mem_cmd_ready), .inspect_mem_rsp_valid(inspect_mem_rsp_valid), .inspect_mem_rsp_ready(inspect_mem_rsp_ready), .inspect_core_clk(inspect_core_clk), .core_csr_clk(core_csr_clk), .core_wfi(core_wfi), .tm_stop(tm_stop), .pc_rtvec(pc_rtvec), .dbg_irq_r(dbg_irq_r), .cmt_dpc(cmt_dpc), .cmt_dpc_ena(cmt_dpc_ena), .cmt_dcause(cmt_dcause), .cmt_dcause_ena(cmt_dcause_ena), .wr_dcsr_ena(wr_dcsr_ena), .wr_dpc_ena(wr_dpc_ena), .wr_dscratch_ena(wr_dscratch_ena), .wr_csr_nxt(wr_csr_nxt), .dcsr_r(dcsr_r), .dpc_r(dpc_r), .dscratch_r(dscratch_r), .dbg_mode(dbg_mode), .dbg_halt_r(dbg_halt_r), .dbg_step_r(dbg_step_r), .dbg_ebreakm_r(dbg_ebreakm_r), .dbg_stopcycle(dbg_stopcycle), .dbg_irq_a(dbg_irq_a), .core_mhartid(core_mhartid), .ext_irq_a(ext_irq_a), .sft_irq_a(sft_irq_a), .tmr_irq_a(tmr_irq_a), .tcm_sd(tcm_sd), .tcm_ds(tcm_ds), .ext2itcm_icb_cmd_valid(ext2itcm_icb_cmd_valid), .ext2itcm_icb_cmd_ready(ext2itcm_icb_cmd_ready), .ext2itcm_icb_cmd_addr(ext2itcm_icb_cmd_addr), .ext2itcm_icb_cmd_read(ext2itcm_icb_cmd_read), .ext2itcm_icb_cmd_wdata(ext2itcm_icb_cmd_wdata), .ext2itcm_icb_cmd_wmask(ext2itcm_icb_cmd_wmask), .ext2itcm_icb_rsp_valid(ext2itcm_icb_rsp_valid), .ext2itcm_icb_rsp_ready(ext2itcm_icb_rsp_ready), .ext2itcm_icb_rsp_err(ext2itcm_icb_rsp_err), .ext2itcm_icb_rsp_rdata(ext2itcm_icb_rsp_rdata), .ext2dtcm_icb_cmd_valid(ext2dtcm_icb_cmd_valid), .ext2dtcm_icb_cmd_ready(ext2dtcm_icb_cmd_ready), .ext2dtcm_icb_cmd_addr(ext2dtcm_icb_cmd_addr), .ext2dtcm_icb_cmd_read(ext2dtcm_icb_cmd_read), .ext2dtcm_icb_cmd_wdata(ext2dtcm_icb_cmd_wdata), .ext2dtcm_icb_cmd_wmask(ext2dtcm_icb_cmd_wmask), .ext2dtcm_icb_rsp_valid(ext2dtcm_icb_rsp_valid), .ext2dtcm_icb_rsp_ready(ext2dtcm_icb_rsp_ready), .ext2dtcm_icb_rsp_err(ext2dtcm_icb_rsp_err), .ext2dtcm_icb_rsp_rdata(ext2dtcm_icb_rsp_rdata), .ppi_icb_cmd_valid(ppi_icb_cmd_valid), .ppi_icb_cmd_ready(ppi_icb_cmd_ready), .ppi_icb_cmd_addr(ppi_icb_cmd_addr), .ppi_icb_cmd_read(ppi_icb_cmd_read), .ppi_icb_cmd_wdata(ppi_icb_cmd_wdata), .ppi_icb_cmd_wmask(ppi_icb_cmd_wmask), .ppi_icb_rsp_valid(ppi_icb_rsp_valid), .ppi_icb_rsp_ready(ppi_icb_rsp_ready), .ppi_icb_rsp_err(ppi_icb_rsp_err), .ppi_icb_rsp_rdata(ppi_icb_rsp_rdata), .clint_icb_cmd_valid(clint_icb_cmd_valid), .clint_icb_cmd_ready(clint_icb_cmd_ready), .clint_icb_cmd_addr(clint_icb_cmd_addr), .clint_icb_cmd_read(clint_icb_cmd_read), .clint_icb_cmd_wdata(clint_icb_cmd_wdata), .clint_icb_cmd_wmask(clint_icb_cmd_wmask), .clint_icb_rsp_valid(clint_icb_rsp_valid), .clint_icb_rsp_ready(clint_icb_rsp_ready), .clint_icb_rsp_err(clint_icb_rsp_err), .clint_icb_rsp_rdata(clint_icb_rsp_rdata), .plic_icb_cmd_valid(plic_icb_cmd_valid), .plic_icb_cmd_ready(plic_icb_cmd_ready), .plic_icb_cmd_addr(plic_icb_cmd_addr), .plic_icb_cmd_read(plic_icb_cmd_read), .plic_icb_cmd_wdata(plic_icb_cmd_wdata), .plic_icb_cmd_wmask(plic_icb_cmd_wmask), .plic_icb_rsp_valid(plic_icb_rsp_valid), .plic_icb_rsp_ready(plic_icb_rsp_ready), .plic_icb_rsp_err(plic_icb_rsp_err), .plic_icb_rsp_rdata(plic_icb_rsp_rdata), .fio_icb_cmd_valid(fio_icb_cmd_valid), .fio_icb_cmd_ready(fio_icb_cmd_ready), .fio_icb_cmd_addr(fio_icb_cmd_addr), .fio_icb_cmd_read(fio_icb_cmd_read), .fio_icb_cmd_wdata(fio_icb_cmd_wdata), .fio_icb_cmd_wmask(fio_icb_cmd_wmask), .fio_icb_rsp_valid(fio_icb_rsp_valid), .fio_icb_rsp_ready(fio_icb_rsp_ready), .fio_icb_rsp_err(fio_icb_rsp_err), .fio_icb_rsp_rdata(fio_icb_rsp_rdata), .mem_icb_cmd_valid(mem_icb_cmd_valid), .mem_icb_cmd_ready(mem_icb_cmd_ready), .mem_icb_cmd_addr(mem_icb_cmd_addr), .mem_icb_cmd_read(mem_icb_cmd_read), .mem_icb_cmd_wdata(mem_icb_cmd_wdata), .mem_icb_cmd_wmask(mem_icb_cmd_wmask), .mem_icb_rsp_valid(mem_icb_rsp_valid), .mem_icb_rsp_ready(mem_icb_rsp_ready), .mem_icb_rsp_err(mem_icb_rsp_err), .mem_icb_rsp_rdata(mem_icb_rsp_rdata), .test_mode(test_mode), .clk(clk), .rst_n(rst_n));
initial begin
clk = 1'b0;
forever #5 clk = ~clk;
end
initial begin
seed = 20260419;
$dumpfile("e203_cpu_top_auto.vcd");
$dumpvars(0, tb_e203_cpu_top_auto);
pc_rtvec = 1'd0;
dcsr_r = 1'd0;
dpc_r = 1'd0;
dscratch_r = 1'd0;
dbg_mode = 1'd0;
dbg_halt_r = 1'd0;
dbg_step_r = 1'd0;
dbg_ebreakm_r = 1'd0;
dbg_stopcycle = 1'd0;
dbg_irq_a = 1'd0;
core_mhartid = 1'd0;
ext_irq_a = 1'd0;
sft_irq_a = 1'd0;
tmr_irq_a = 1'd0;
tcm_sd = 1'd0;
tcm_ds = 1'd0;
ext2itcm_icb_cmd_valid = 1'd0;
ext2itcm_icb_cmd_addr = 1'd0;
ext2itcm_icb_cmd_read = 1'd0;
ext2itcm_icb_cmd_wdata = 1'd0;
ext2itcm_icb_cmd_wmask = 1'd0;
ext2itcm_icb_rsp_ready = 1'd0;
ext2dtcm_icb_cmd_valid = 1'd0;
ext2dtcm_icb_cmd_addr = 1'd0;
ext2dtcm_icb_cmd_read = 1'd0;
ext2dtcm_icb_cmd_wdata = 1'd0;
ext2dtcm_icb_cmd_wmask = 1'd0;
ext2dtcm_icb_rsp_ready = 1'd0;
ppi_icb_cmd_ready = 1'd0;
ppi_icb_rsp_valid = 1'd0;
ppi_icb_rsp_err = 1'd0;
ppi_icb_rsp_rdata = 1'd0;
clint_icb_cmd_ready = 1'd0;
clint_icb_rsp_valid = 1'd0;
clint_icb_rsp_err = 1'd0;
clint_icb_rsp_rdata = 1'd0;
plic_icb_cmd_ready = 1'd0;
plic_icb_rsp_valid = 1'd0;
plic_icb_rsp_err = 1'd0;
plic_icb_rsp_rdata = 1'd0;
fio_icb_cmd_ready = 1'd0;
fio_icb_rsp_valid = 1'd0;
fio_icb_rsp_err = 1'd0;
fio_icb_rsp_rdata = 1'd0;
mem_icb_cmd_ready = 1'd0;
mem_icb_rsp_valid = 1'd0;
mem_icb_rsp_err = 1'd0;
mem_icb_rsp_rdata = 1'd0;
test_mode = 1'd0;
rst_n = 1'b0;
repeat (2) @(posedge clk);
rst_n = 1'b1;
for (i = 0; i < 8; i = i + 1) begin
@(negedge clk);
pc_rtvec = $random(seed) & 1'd1;
dcsr_r = $random(seed) & 1'd1;
dpc_r = $random(seed) & 1'd1;
dscratch_r = $random(seed) & 1'd1;
dbg_mode = $random(seed) & 1'd1;
dbg_halt_r = $random(seed) & 1'd1;
dbg_step_r = $random(seed) & 1'd1;
dbg_ebreakm_r = $random(seed) & 1'd1;
dbg_stopcycle = $random(seed) & 1'd1;
dbg_irq_a = $random(seed) & 1'd1;
core_mhartid = $random(seed) & 1'd1;
ext_irq_a = $random(seed) & 1'd1;
sft_irq_a = $random(seed) & 1'd1;
tmr_irq_a = $random(seed) & 1'd1;
tcm_sd = $random(seed) & 1'd1;
tcm_ds = $random(seed) & 1'd1;
ext2itcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2itcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2itcm_icb_cmd_read = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2itcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2itcm_icb_rsp_ready = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_valid = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_addr = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_read = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wdata = $random(seed) & 1'd1;
ext2dtcm_icb_cmd_wmask = $random(seed) & 1'd1;
ext2dtcm_icb_rsp_ready = $random(seed) & 1'd1;
ppi_icb_cmd_ready = $random(seed) & 1'd1;
ppi_icb_rsp_valid = $random(seed) & 1'd1;
ppi_icb_rsp_err = $random(seed) & 1'd1;
ppi_icb_rsp_rdata = $random(seed) & 1'd1;
clint_icb_cmd_ready = $random(seed) & 1'd1;
clint_icb_rsp_valid = $random(seed) & 1'd1;
clint_icb_rsp_err = $random(seed) & 1'd1;
clint_icb_rsp_rdata = $random(seed) & 1'd1;
plic_icb_cmd_ready = $random(seed) & 1'd1;
plic_icb_rsp_valid = $random(seed) & 1'd1;
plic_icb_rsp_err = $random(seed) & 1'd1;
plic_icb_rsp_rdata = $random(seed) & 1'd1;
fio_icb_cmd_ready = $random(seed) & 1'd1;
fio_icb_rsp_valid = $random(seed) & 1'd1;
fio_icb_rsp_err = $random(seed) & 1'd1;
fio_icb_rsp_rdata = $random(seed) & 1'd1;
mem_icb_cmd_ready = $random(seed) & 1'd1;
mem_icb_rsp_valid = $random(seed) & 1'd1;
mem_icb_rsp_err = $random(seed) & 1'd1;
mem_icb_rsp_rdata = $random(seed) & 1'd1;
test_mode = $random(seed) & 1'd1;
@(posedge clk);
end
#1;
$finish;
end
endmodule

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{
"timestamp_utc": "2026-04-19T06:38:06.434830+00:00",
"repo_root": "/Users/ningyedong/Coding/Verilog-Learn",
"workspace": "/private/tmp/chipverify_github_cpu_example",
"projects_file": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/projects.json",
"tool": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py",
"results": [
{
"name": "ultraembedded_riscv_core",
"repo": "https://github.com/ultraembedded/riscv.git",
"stars": 1703,
"status": "pass",
"clone_status": "updated",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv",
"top": "riscv_core",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/run.log"
}
},
{
"name": "zipcpu",
"repo": "https://github.com/ZipCPU/zipcpu.git",
"stars": 1535,
"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl",
"top": "zipcore",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/run.log"
}
},
{
"name": "e203_cpu_top_fullrtl",
"repo": "https://github.com/riscv-mcu/e203_hbirdv2.git",
"stars": 1811,
"status": "pass",
"clone_status": "cloned",
"rtl_dir": "/private/tmp/chipverify_github_cpu_example/clones/e203_cpu_top_fullrtl/rtl",
"top": "e203_cpu_top",
"return_code": 0,
"artifacts": {
"tb": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/tb_e203_cpu_top_auto.v",
"vcd": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/e203_cpu_top_auto.vcd",
"sim_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/sim_output.log",
"sim_binary": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/auto_sim.out",
"run_log": "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/e203_cpu_top_fullrtl/run.log"
}
}
],
"pass_count": 3,
"fail_count": 0,
"total": 3
}

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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv --top riscv_core --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core --cycles 12 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 18 Verilog files
Selected top module: riscv_core
Top module file: /private/tmp/chipverify_github_cpu_example/clones/ultraembedded_riscv_core/core/riscv/riscv_core.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/riscv_core_auto.vcd
STDERR:

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VCD info: dumpfile riscv_core_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/ultraembedded_riscv_core/tb_riscv_core_auto.v:71: $finish called at 12000 (1ps)

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`timescale 1ns/1ps
module tb_riscv_core_auto;
reg clk_i;
reg rst_i;
reg [31:0] mem_d_data_rd_i;
reg mem_d_accept_i;
reg mem_d_ack_i;
reg mem_d_error_i;
reg [10:0] mem_d_resp_tag_i;
reg mem_i_accept_i;
reg mem_i_valid_i;
reg mem_i_error_i;
reg [31:0] mem_i_inst_i;
reg intr_i;
reg [31:0] reset_vector_i;
reg [31:0] cpu_id_i;
wire [31:0] mem_d_addr_o;
wire [31:0] mem_d_data_wr_o;
wire mem_d_rd_o;
wire [3:0] mem_d_wr_o;
wire mem_d_cacheable_o;
wire [10:0] mem_d_req_tag_o;
wire mem_d_invalidate_o;
wire mem_d_writeback_o;
wire mem_d_flush_o;
wire mem_i_rd_o;
wire mem_i_flush_o;
wire mem_i_invalidate_o;
wire [31:0] mem_i_pc_o;
integer i;
integer seed;
integer vec;
riscv_core dut (.clk_i(clk_i), .rst_i(rst_i), .mem_d_data_rd_i(mem_d_data_rd_i), .mem_d_accept_i(mem_d_accept_i), .mem_d_ack_i(mem_d_ack_i), .mem_d_error_i(mem_d_error_i), .mem_d_resp_tag_i(mem_d_resp_tag_i), .mem_i_accept_i(mem_i_accept_i), .mem_i_valid_i(mem_i_valid_i), .mem_i_error_i(mem_i_error_i), .mem_i_inst_i(mem_i_inst_i), .intr_i(intr_i), .reset_vector_i(reset_vector_i), .cpu_id_i(cpu_id_i), .mem_d_addr_o(mem_d_addr_o), .mem_d_data_wr_o(mem_d_data_wr_o), .mem_d_rd_o(mem_d_rd_o), .mem_d_wr_o(mem_d_wr_o), .mem_d_cacheable_o(mem_d_cacheable_o), .mem_d_req_tag_o(mem_d_req_tag_o), .mem_d_invalidate_o(mem_d_invalidate_o), .mem_d_writeback_o(mem_d_writeback_o), .mem_d_flush_o(mem_d_flush_o), .mem_i_rd_o(mem_i_rd_o), .mem_i_flush_o(mem_i_flush_o), .mem_i_invalidate_o(mem_i_invalidate_o), .mem_i_pc_o(mem_i_pc_o));
initial begin
seed = 20260419;
$dumpfile("riscv_core_auto.vcd");
$dumpvars(0, tb_riscv_core_auto);
clk_i = 1'd0;
mem_d_data_rd_i = 32'd0;
mem_d_accept_i = 1'd0;
mem_d_ack_i = 1'd0;
mem_d_error_i = 1'd0;
mem_d_resp_tag_i = 11'd0;
mem_i_accept_i = 1'd0;
mem_i_valid_i = 1'd0;
mem_i_error_i = 1'd0;
mem_i_inst_i = 32'd0;
intr_i = 1'd0;
reset_vector_i = 32'd0;
cpu_id_i = 32'd0;
rst_i = 1'b1;
for (i = 0; i < 12; i = i + 1) begin
clk_i = $random(seed) & 1'd1;
mem_d_data_rd_i = $random(seed) & 32'd4294967295;
mem_d_accept_i = $random(seed) & 1'd1;
mem_d_ack_i = $random(seed) & 1'd1;
mem_d_error_i = $random(seed) & 1'd1;
mem_d_resp_tag_i = $random(seed) & 11'd2047;
mem_i_accept_i = $random(seed) & 1'd1;
mem_i_valid_i = $random(seed) & 1'd1;
mem_i_error_i = $random(seed) & 1'd1;
mem_i_inst_i = $random(seed) & 32'd4294967295;
intr_i = $random(seed) & 1'd1;
reset_vector_i = $random(seed) & 32'd4294967295;
cpu_id_i = $random(seed) & 32'd4294967295;
#1;
end
$finish;
end
endmodule

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COMMAND:
/opt/anaconda3/bin/python /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/one_click_verify.py --dir /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl --top zipcore --out /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu --cycles 12 --period 10 --reset-cycles 2
STDOUT:
=== ChipVerify One-Click Auto Verification ===
Found 51 Verilog files
Selected top module: zipcore
Top module file: /private/tmp/chipverify_github_cpu_example/clones/zipcpu/rtl/core/zipcore.v
Generated testbench: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v
Simulation completed successfully
Simulation binary: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/auto_sim.out
Waveform: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
Simulation log: /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/sim_output.log
Open waveform with: gtkwave /Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/zipcore_auto.vcd
STDERR:

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VCD info: dumpfile zipcore_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/examples/github_cpu_validation/results/zipcpu/tb_zipcore_auto.v:106: $finish called at 136000 (1ps)

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`timescale 1ns/1ps
module tb_zipcore_auto;
reg i_clk;
reg i_reset;
reg i_interrupt;
reg i_halt;
reg i_clear_cache;
reg [4:0] i_dbg_wreg;
reg i_dbg_we;
reg [31:0] i_dbg_data;
reg [4:0] i_dbg_rreg;
reg i_pf_valid;
reg i_pf_illegal;
reg [31:0] i_pf_instruction;
reg i_pf_instruction_pc;
reg i_mem_busy;
reg i_mem_rdbusy;
reg i_mem_pipe_stalled;
reg i_mem_valid;
reg i_bus_err;
reg [4:0] i_mem_wreg;
reg [31:0] i_mem_result;
wire o_clken;
wire o_dbg_stall;
wire [31:0] o_dbg_reg;
wire [2:0] o_dbg_cc;
wire o_break;
wire o_pf_new_pc;
wire o_clear_icache;
wire o_pf_ready;
wire o_pf_request_address;
wire o_clear_dcache;
wire o_mem_ce;
wire o_bus_lock;
wire [2:0] o_mem_op;
wire [31:0] o_mem_addr;
wire [31:0] o_mem_data;
wire o_mem_lock_pc;
wire [4:0] o_mem_reg;
wire o_op_stall;
wire o_pf_stall;
wire o_i_count;
wire [31:0] o_debug;
wire o_prof_stb;
wire o_prof_addr;
wire [31:0] o_prof_ticks;
integer i;
integer seed;
zipcore dut (.i_clk(i_clk), .i_reset(i_reset), .i_interrupt(i_interrupt), .o_clken(o_clken), .i_halt(i_halt), .i_clear_cache(i_clear_cache), .i_dbg_wreg(i_dbg_wreg), .i_dbg_we(i_dbg_we), .i_dbg_data(i_dbg_data), .i_dbg_rreg(i_dbg_rreg), .o_dbg_stall(o_dbg_stall), .o_dbg_reg(o_dbg_reg), .o_dbg_cc(o_dbg_cc), .o_break(o_break), .o_pf_new_pc(o_pf_new_pc), .o_clear_icache(o_clear_icache), .o_pf_ready(o_pf_ready), .o_pf_request_address(o_pf_request_address), .i_pf_valid(i_pf_valid), .i_pf_illegal(i_pf_illegal), .i_pf_instruction(i_pf_instruction), .i_pf_instruction_pc(i_pf_instruction_pc), .o_clear_dcache(o_clear_dcache), .o_mem_ce(o_mem_ce), .o_bus_lock(o_bus_lock), .o_mem_op(o_mem_op), .o_mem_addr(o_mem_addr), .o_mem_data(o_mem_data), .o_mem_lock_pc(o_mem_lock_pc), .o_mem_reg(o_mem_reg), .i_mem_busy(i_mem_busy), .i_mem_rdbusy(i_mem_rdbusy), .i_mem_pipe_stalled(i_mem_pipe_stalled), .i_mem_valid(i_mem_valid), .i_bus_err(i_bus_err), .i_mem_wreg(i_mem_wreg), .i_mem_result(i_mem_result), .o_op_stall(o_op_stall), .o_pf_stall(o_pf_stall), .o_i_count(o_i_count), .o_debug(o_debug), .o_prof_stb(o_prof_stb), .o_prof_addr(o_prof_addr), .o_prof_ticks(o_prof_ticks));
initial begin
i_clk = 1'b0;
forever #5 i_clk = ~i_clk;
end
initial begin
seed = 20260419;
$dumpfile("zipcore_auto.vcd");
$dumpvars(0, tb_zipcore_auto);
i_interrupt = 1'd0;
i_halt = 1'd0;
i_clear_cache = 1'd0;
i_dbg_wreg = 5'd0;
i_dbg_we = 1'd0;
i_dbg_data = 32'd0;
i_dbg_rreg = 5'd0;
i_pf_valid = 1'd0;
i_pf_illegal = 1'd0;
i_pf_instruction = 32'd0;
i_pf_instruction_pc = 1'd0;
i_mem_busy = 1'd0;
i_mem_rdbusy = 1'd0;
i_mem_pipe_stalled = 1'd0;
i_mem_valid = 1'd0;
i_bus_err = 1'd0;
i_mem_wreg = 5'd0;
i_mem_result = 32'd0;
i_reset = 1'b1;
repeat (2) @(posedge i_clk);
i_reset = 1'b0;
for (i = 0; i < 12; i = i + 1) begin
@(negedge i_clk);
i_interrupt = $random(seed) & 1'd1;
i_halt = $random(seed) & 1'd1;
i_clear_cache = $random(seed) & 1'd1;
i_dbg_wreg = $random(seed) & 5'd31;
i_dbg_we = $random(seed) & 1'd1;
i_dbg_data = $random(seed) & 32'd4294967295;
i_dbg_rreg = $random(seed) & 5'd31;
i_pf_valid = $random(seed) & 1'd1;
i_pf_illegal = $random(seed) & 1'd1;
i_pf_instruction = $random(seed) & 32'd4294967295;
i_pf_instruction_pc = $random(seed) & 1'd1;
i_mem_busy = $random(seed) & 1'd1;
i_mem_rdbusy = $random(seed) & 1'd1;
i_mem_pipe_stalled = $random(seed) & 1'd1;
i_mem_valid = $random(seed) & 1'd1;
i_bus_err = $random(seed) & 1'd1;
i_mem_wreg = $random(seed) & 5'd31;
i_mem_result = $random(seed) & 32'd4294967295;
@(posedge i_clk);
end
#1;
$finish;
end
endmodule

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#!/usr/bin/env python3
"""验证 SLWChipVerify 在热门开源 GitHub CPU 项目上的一键流程可用性。"""
from __future__ import annotations
import argparse
import json
import shutil
import subprocess
import sys
from dataclasses import dataclass
from datetime import datetime, timezone
from pathlib import Path
from typing import Any
@dataclass
class ProjectCase:
"""描述一个待验证项目的仓库信息与仿真参数。"""
name: str
repo: str
stars: int
rtl_subdir: str
top: str
cycles: int
period: int
reset_cycles: int
def _run(cmd: list[str], cwd: Path | None = None) -> subprocess.CompletedProcess[str]:
"""执行外部命令并收集标准输出/标准错误。"""
return subprocess.run(
cmd,
cwd=str(cwd) if cwd is not None else None,
text=True,
capture_output=True,
check=False,
)
def _load_cases(path: Path) -> list[ProjectCase]:
"""从 JSON 文件加载项目清单。"""
raw: list[dict[str, Any]] = json.loads(path.read_text(encoding="utf-8"))
cases: list[ProjectCase] = []
for item in raw:
cases.append(
ProjectCase(
name=str(item["name"]),
repo=str(item["repo"]),
stars=int(item["stars"]),
rtl_subdir=str(item["rtl_subdir"]),
top=str(item["top"]),
cycles=int(item["cycles"]),
period=int(item["period"]),
reset_cycles=int(item["reset_cycles"]),
)
)
return cases
def _clone_or_update(case: ProjectCase, clone_dir: Path) -> tuple[bool, str]:
"""克隆仓库，或对已有仓库做浅拉取并硬重置到远端最新状态。"""
if clone_dir.exists() and (clone_dir / ".git").exists():
fetch = _run(["git", "-C", str(clone_dir), "fetch", "--depth", "1", "origin"])
if fetch.returncode != 0:
return False, fetch.stderr.strip() or fetch.stdout.strip()
reset = _run(["git", "-C", str(clone_dir), "reset", "--hard", "origin/HEAD"])
if reset.returncode != 0:
return False, reset.stderr.strip() or reset.stdout.strip()
return True, "updated"
if clone_dir.exists():
shutil.rmtree(clone_dir)
clone_dir.parent.mkdir(parents=True, exist_ok=True)
clone = _run(["git", "clone", "--depth", "1", case.repo, str(clone_dir)])
if clone.returncode != 0:
return False, clone.stderr.strip() or clone.stdout.strip()
return True, "cloned"
def main() -> int:
"""按项目列表逐个执行一键验证，并输出汇总 JSON 报告。"""
script_dir = Path(__file__).resolve().parent
default_repo_root = script_dir.parents[2]
parser = argparse.ArgumentParser(description="运行 SLWChipVerify GitHub CPU 验证示例")
parser.add_argument(
"--repo-root",
default=str(default_repo_root),
help="Path to Verilog-Learn repository root",
)
parser.add_argument(
"--projects",
default=str(script_dir / "projects.json"),
help="Path to project case JSON",
)
parser.add_argument(
"--workspace",
default="/tmp/slwchipverify_github_cpu_example",
help="Temporary clone workspace",
)
parser.add_argument(
"--results-dir",
default=str(script_dir / "results"),
help="Directory to store per-case outputs and summary",
)
parser.add_argument(
"--python",
default=sys.executable,
help="Python executable used to run one_click_verify.py",
)
args = parser.parse_args()
repo_root = Path(args.repo_root).expanduser().resolve()
one_click = repo_root / "slwchipverify" / "one_click_verify.py"
if not one_click.exists():
print(
f"[SLWChipVerify][github-example] ERROR: one_click script not found: {one_click}",
file=sys.stderr,
)
return 2
project_file = Path(args.projects).expanduser().resolve()
cases = _load_cases(project_file)
workspace = Path(args.workspace).expanduser().resolve()
clones_dir = workspace / "clones"
results_dir = Path(args.results_dir).expanduser().resolve()
results_dir.mkdir(parents=True, exist_ok=True)
summary: dict[str, Any] = {
"timestamp_utc": datetime.now(timezone.utc).isoformat(),
"repo_root": str(repo_root),
"workspace": str(workspace),
"projects_file": str(project_file),
"tool": str(one_click),
"results": [],
}
pass_count = 0
fail_count = 0
for case in cases:
print(f"\\n=== Case: {case.name} ===")
clone_dir = clones_dir / case.name
ok, clone_msg = _clone_or_update(case, clone_dir)
if not ok:
fail_count += 1
result = {
"name": case.name,
"repo": case.repo,
"stars": case.stars,
"status": "fail",
"stage": "clone",
"error": clone_msg,
}
summary["results"].append(result)
print(f"[SLWChipVerify][github-example] FAIL clone: {clone_msg}")
continue
target_dir = (clone_dir / case.rtl_subdir).resolve()
out_dir = results_dir / case.name
if out_dir.exists():
shutil.rmtree(out_dir)
out_dir.mkdir(parents=True, exist_ok=True)
cmd = [
args.python,
str(one_click),
"--dir",
str(target_dir),
"--top",
case.top,
"--out",
str(out_dir),
"--cycles",
str(case.cycles),
"--period",
str(case.period),
"--reset-cycles",
str(case.reset_cycles),
]
run = _run(cmd)
run_log = out_dir / "run.log"
run_log.write_text(
"COMMAND:\n"
+ " ".join(cmd)
+ "\n\nSTDOUT:\n"
+ run.stdout
+ "\n\nSTDERR:\n"
+ run.stderr,
encoding="utf-8",
)
artifacts = {
"tb": str(next(iter(sorted(out_dir.glob("tb_*_auto.v"))), "")),
"vcd": str(next(iter(sorted(out_dir.glob("*_auto.vcd"))), "")),
"sim_log": str(out_dir / "sim_output.log") if (out_dir / "sim_output.log").exists() else "",
"sim_binary": str(out_dir / "auto_sim.out") if (out_dir / "auto_sim.out").exists() else "",
"run_log": str(run_log),
}
status = "pass" if run.returncode == 0 else "fail"
if status == "pass":
pass_count += 1
print("[SLWChipVerify][github-example] PASS")
else:
fail_count += 1
print(f"[SLWChipVerify][github-example] FAIL (exit={run.returncode})")
result = {
"name": case.name,
"repo": case.repo,
"stars": case.stars,
"status": status,
"clone_status": clone_msg,
"rtl_dir": str(target_dir),
"top": case.top,
"return_code": run.returncode,
"artifacts": artifacts,
}
if status == "fail":
result["error_tail"] = (run.stderr or run.stdout)[-2000:]
summary["results"].append(result)
summary["pass_count"] = pass_count
summary["fail_count"] = fail_count
summary["total"] = len(cases)
summary_path = results_dir / "github_cpu_validation_summary.json"
summary_path.write_text(json.dumps(summary, ensure_ascii=False, indent=2), encoding="utf-8")
print("\\n=== Summary ===")
print(f"Passed: {pass_count}")
print(f"Failed: {fail_count}")
print(f"Summary: {summary_path}")
return 0 if fail_count == 0 else 1
if __name__ == "__main__":
raise SystemExit(main())

16
examples/seq_auto_demo.v Normal file
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// SLWChipVerify 时序验证示例：
// 在时钟上升沿把输入 din 锁存到输出 q；复位时清零 q。
module seq_auto_demo(
input clk,
input rst,
input [1:0] din,
output reg [1:0] q
);
// 该寄存器逻辑用于演示自动时序激励与断言检查。
always @(posedge clk or posedge rst) begin
if (rst)
q <= 2'd0;
else
q <= din;
end
endmodule

61
examples/seq_auto_demo_spec.json Normal file
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{
"kind": "sequential",
"clock": {
"name": "clk",
"period_ns": 10,
"initial": 0
},
"reset": {
"name": "rst",
"active": 1,
"cycles": 1
},
"inputs": [
{
"name": "din",
"width": 2
}
],
"outputs": [
{
"name": "q",
"width": 2
}
],
"max_cycles": 5,
"auto_stimulus": {
"enabled": true,
"start_cycle": 0,
"mode": "binary_count"
},
"assertions": [
{
"name": "rst_cycle0",
"cycle": 0,
"expect": {
"q": 0
}
},
{
"name": "q_cycle1",
"cycle": 1,
"expect": {
"q": 1
}
},
{
"name": "q_cycle2",
"cycle": 2,
"expect": {
"q": 2
}
},
{
"name": "q_cycle3",
"cycle": 3,
"expect": {
"q": 3
}
}
]
}

51
examples/seq_random_demo_spec.json Normal file
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@@ -0,0 +1,51 @@
{
"kind": "sequential",
"clock": {
"name": "clk",
"period_ns": 10,
"initial": 0
},
"reset": {
"name": "rst",
"active": 1,
"cycles": 1
},
"inputs": [
{
"name": "din",
"width": 2
}
],
"outputs": [
{
"name": "q",
"width": 2
}
],
"max_cycles": 8,
"auto_stimulus": {
"enabled": true,
"start_cycle": 0,
"mode": "random",
"seed": 20260419
},
"assertions": [
{
"name": "reset_cycle0",
"cycle": 0,
"expect": {
"q": 0
}
},
{
"name": "q_range_guard",
"cycle": 1,
"expect": {
"q": {
"op": "le",
"value": 3
}
}
}
]
}

44
examples/simple_cpu_eventually_spec.json Normal file
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{
"kind": "sequential",
"clock": {
"name": "clk",
"period_ns": 10,
"initial": 0
},
"reset": {
"name": "rst",
"active": 1,
"cycles": 2
},
"inputs": [],
"outputs": [],
"observes": [
{
"name": "cnt",
"expr": "dut.cnt",
"width": 4
}
],
"max_cycles": 7,
"auto_stimulus": {
"enabled": false
},
"assertions": [
{
"name": "count_cycle2",
"cycle": 2,
"expect": {
"cnt": 1
}
},
{
"name": "eventually_cnt_3",
"cycle": 2,
"mode": "eventually",
"within": 2,
"expect": {
"cnt": 3
}
}
]
}

63
examples/simple_cpu_seq_spec.json Normal file
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{
"kind": "sequential",
"clock": {
"name": "clk",
"period_ns": 10,
"initial": 0
},
"reset": {
"name": "rst",
"active": 1,
"cycles": 2
},
"inputs": [],
"outputs": [],
"observes": [
{
"name": "cnt",
"expr": "dut.cnt",
"width": 4
}
],
"max_cycles": 6,
"auto_stimulus": {
"enabled": false
},
"assertions": [
{
"name": "reset_cycle0",
"cycle": 0,
"expect": {
"cnt": 0
}
},
{
"name": "reset_cycle1",
"cycle": 1,
"expect": {
"cnt": 0
}
},
{
"name": "count_cycle2",
"cycle": 2,
"expect": {
"cnt": 1
}
},
{
"name": "count_cycle3",
"cycle": 3,
"expect": {
"cnt": 2
}
},
{
"name": "count_cycle4",
"cycle": 4,
"expect": {
"cnt": 3
}
}
]
}

71
examples/simple_cpu_window_modes_spec.json Normal file
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{
"kind": "sequential",
"clock": {
"name": "clk",
"period_ns": 10,
"initial": 0
},
"reset": {
"name": "rst",
"active": 1,
"cycles": 2
},
"inputs": [],
"outputs": [],
"observes": [
{
"name": "cnt",
"expr": "dut.cnt",
"width": 4
}
],
"max_cycles": 7,
"auto_stimulus": {
"enabled": false
},
"assertions": [
{
"name": "cycle_cnt_1",
"cycle": 2,
"expect": {
"cnt": 1
}
},
{
"name": "always_cnt_ge_1",
"cycle": 2,
"mode": "always",
"within": 2,
"expect": {
"cnt": {
"op": "ge",
"value": 1
}
}
},
{
"name": "never_cnt_eq_0",
"cycle": 2,
"mode": "never",
"within": 2,
"expect": {
"cnt": 0
}
},
{
"name": "until_cnt_lt_4_until_4",
"cycle": 2,
"mode": "until",
"within": 3,
"expect": {
"cnt": {
"op": "lt",
"value": 4
}
},
"until_expect": {
"cnt": 4
}
}
]
}