ningyd/SLWChipVerify
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Init Push

Browse Source
This commit is contained in:
ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
54 changed files with 80296 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
auto_single_check/sim_output.log Normal file
View File

@@ -0,0 +1,2 @@
VCD info: dumpfile simple_cpu_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_single_check/tb_simple_cpu_auto.v:27: $finish called at 76000 (1ps)