ningyd/SLWChipVerify
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ningyd
2026-04-19 16:14:05 +08:00
commit 5b6bd1ac23
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auto_out_simple_cpu/sim_output.log Normal file
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VCD info: dumpfile simple_cpu_auto.vcd opened for output.
/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_out_simple_cpu/tb_simple_cpu_auto.v:27: $finish called at 216000 (1ps)