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100
auto_out_simple_cpu/auto_sim.out
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100
auto_out_simple_cpu/auto_sim.out
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#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
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:ivl_version "13.0 (stable)" "(v13_0)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
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:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
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S_0x1031a0ba0 .scope package, "$unit" "$unit" 2 1;
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.timescale 0 0;
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S_0x10319f1c0 .scope module, "tb_simple_cpu_auto" "tb_simple_cpu_auto" 3 2;
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.timescale -9 -12;
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v0x1031a5580_0 .var "clk", 0 0;
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v0x1031a5620_0 .var/i "i", 31 0;
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v0x1031a56c0_0 .var "rst", 0 0;
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v0x1031a5760_0 .var/i "seed", 31 0;
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E_0x1031a49f0 .event posedge, v0x1031a0d20_0;
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S_0x10319f340 .scope module, "dut" "simple_cpu" 3 9, 4 1 0, S_0x10319f1c0;
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.timescale 0 0;
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.port_info 0 /INPUT 1 "clk";
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.port_info 1 /INPUT 1 "rst";
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v0x1031a0d20_0 .net "clk", 0 0, v0x1031a5580_0; 1 drivers
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v0x10319cf30_0 .var "cnt", 3 0;
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v0x10319cfe0_0 .net "rst", 0 0, v0x1031a56c0_0; 1 drivers
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E_0x10319faf0 .event posedge, v0x10319cfe0_0, v0x1031a0d20_0;
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.scope S_0x10319f340;
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T_0 ;
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%wait E_0x10319faf0;
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%load/vec4 v0x10319cfe0_0;
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%flag_set/vec4 8;
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%jmp/0xz T_0.0, 8;
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%pushi/vec4 0, 0, 4;
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%assign/vec4 v0x10319cf30_0, 0;
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%jmp T_0.1;
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T_0.0 ;
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%load/vec4 v0x10319cf30_0;
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%addi 1, 0, 4;
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%assign/vec4 v0x10319cf30_0, 0;
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T_0.1 ;
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%jmp T_0;
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.thread T_0;
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.scope S_0x10319f1c0;
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T_1 ;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x1031a5580_0, 0, 1;
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T_1.0 ;
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%delay 5000, 0;
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%load/vec4 v0x1031a5580_0;
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%inv;
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%store/vec4 v0x1031a5580_0, 0, 1;
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%jmp T_1.0;
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T_1.1 ;
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%end;
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.thread T_1;
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.scope S_0x10319f1c0;
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T_2 ;
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%pushi/vec4 20260419, 0, 32;
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%store/vec4 v0x1031a5760_0, 0, 32;
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%vpi_call/w 3 18 "$dumpfile", "simple_cpu_auto.vcd" {0 0 0};
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%vpi_call/w 3 19 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x10319f1c0 {0 0 0};
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%pushi/vec4 1, 0, 1;
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%store/vec4 v0x1031a56c0_0, 0, 1;
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%pushi/vec4 2, 0, 32;
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T_2.0 %dup/vec4;
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%cmpi/s 0, 0, 32;
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%jmp/1xz T_2.1, 5;
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%jmp/1 T_2.1, 4;
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%subi 1, 0, 32;
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%wait E_0x1031a49f0;
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%jmp T_2.0;
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T_2.1 ;
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%pop/vec4 1;
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%pushi/vec4 0, 0, 1;
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%store/vec4 v0x1031a56c0_0, 0, 1;
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%pushi/vec4 0, 0, 32;
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%store/vec4 v0x1031a5620_0, 0, 32;
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T_2.2 ; Top of for-loop
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%load/vec4 v0x1031a5620_0;
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%cmpi/s 20, 0, 32;
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%jmp/0xz T_2.3, 5;
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%wait E_0x1031a49f0;
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T_2.4 ; for-loop step statement
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%load/vec4 v0x1031a5620_0;
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%addi 1, 0, 32;
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%store/vec4 v0x1031a5620_0, 0, 32;
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%jmp T_2.2;
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T_2.3 ; for-loop exit label
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%delay 1000, 0;
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%vpi_call/w 3 27 "$finish" {0 0 0};
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%end;
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.thread T_2;
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# The file index is used to find the file name in the following table.
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:file_names 5;
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"N/A";
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"<interactive>";
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"-";
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"/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_out_simple_cpu/tb_simple_cpu_auto.v";
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"/Users/ningyedong/Coding/Verilog-Learn/simple_cpu/simple_cpu.v";
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2
auto_out_simple_cpu/sim_output.log
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2
auto_out_simple_cpu/sim_output.log
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VCD info: dumpfile simple_cpu_auto.vcd opened for output.
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/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_out_simple_cpu/tb_simple_cpu_auto.v:27: $finish called at 216000 (1ps)
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162
auto_out_simple_cpu/simple_cpu_auto.vcd
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162
auto_out_simple_cpu/simple_cpu_auto.vcd
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$date
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Sun Apr 19 14:11:03 2026
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1ps
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$end
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$scope module tb_simple_cpu_auto $end
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$var reg 1 ! clk $end
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$var reg 1 " rst $end
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$var integer 32 # i [31:0] $end
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$var integer 32 $ seed [31:0] $end
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$scope module dut $end
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$var wire 1 ! clk $end
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$var wire 1 " rst $end
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$var reg 4 % cnt [3:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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$comment Show the parameter values. $end
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$dumpall
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$end
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#0
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$dumpvars
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b0 %
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b1001101010010011001000011 $
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bx #
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1"
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0!
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$end
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#5000
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1!
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#10000
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0!
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#15000
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b1 %
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b0 #
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0"
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1!
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#20000
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0!
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#25000
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b10 %
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b1 #
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1!
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#30000
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0!
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#35000
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b11 %
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b10 #
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1!
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#40000
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0!
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#45000
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b100 %
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b11 #
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1!
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#50000
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0!
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#55000
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b101 %
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b100 #
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1!
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#60000
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0!
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#65000
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b110 %
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b101 #
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1!
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#70000
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0!
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#75000
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b111 %
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b110 #
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1!
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#80000
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0!
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#85000
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b1000 %
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b111 #
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1!
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#90000
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0!
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#95000
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b1001 %
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b1000 #
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1!
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#100000
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0!
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#105000
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b1010 %
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b1001 #
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1!
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#110000
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0!
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#115000
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b1011 %
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b1010 #
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1!
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#120000
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0!
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#125000
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b1100 %
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b1011 #
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1!
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#130000
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0!
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#135000
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b1101 %
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b1100 #
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1!
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#140000
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0!
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#145000
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b1110 %
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b1101 #
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1!
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#150000
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0!
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#155000
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b1111 %
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b1110 #
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1!
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#160000
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0!
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#165000
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b0 %
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b1111 #
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1!
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#170000
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0!
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#175000
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b1 %
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b10000 #
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1!
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#180000
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0!
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#185000
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b10 %
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b10001 #
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1!
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#190000
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0!
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#195000
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b11 %
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b10010 #
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1!
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#200000
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0!
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#205000
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b100 %
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b10011 #
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1!
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#210000
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0!
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#215000
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b101 %
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b10100 #
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1!
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#216000
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29
auto_out_simple_cpu/tb_simple_cpu_auto.v
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29
auto_out_simple_cpu/tb_simple_cpu_auto.v
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`timescale 1ns/1ps
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module tb_simple_cpu_auto;
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reg clk;
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reg rst;
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integer i;
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integer seed;
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simple_cpu dut (.clk(clk), .rst(rst));
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initial begin
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clk = 1'b0;
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forever #5 clk = ~clk;
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end
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initial begin
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seed = 20260419;
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$dumpfile("simple_cpu_auto.vcd");
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$dumpvars(0, tb_simple_cpu_auto);
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rst = 1'b1;
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repeat (2) @(posedge clk);
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rst = 1'b0;
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for (i = 0; i < 20; i = i + 1) begin
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@(posedge clk);
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end
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#1;
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$finish;
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end
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endmodule
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