Init Push

auto_out_cli/auto_sim.out

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+#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
+:ivl_version "13.0 (stable)" "(v13_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
+S_0x1016b4c00 .scope package, "$unit" "$unit" 2 1;
+ .timescale 0 0;
+S_0x1016b3190 .scope module, "tb_simple_cpu_auto" "tb_simple_cpu_auto" 3 2;
+ .timescale -9 -12;
+v0x1016b97d0_0 .var "clk", 0 0;
+v0x1016b9870_0 .var/i "i", 31 0;
+v0x1016b9910_0 .var "rst", 0 0;
+v0x1016b99b0_0 .var/i "seed", 31 0;
+E_0x1016b8ca0 .event posedge, v0x1016b4d80_0;
+S_0x1016b3310 .scope module, "dut" "simple_cpu" 3 9, 4 1 0, S_0x1016b3190;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+v0x1016b4d80_0 .net "clk", 0 0, v0x1016b97d0_0;  1 drivers
+v0x1016b0f20_0 .var "cnt", 3 0;
+v0x1016b0fd0_0 .net "rst", 0 0, v0x1016b9910_0;  1 drivers
+E_0x1016b3ac0 .event posedge, v0x1016b0fd0_0, v0x1016b4d80_0;
+    .scope S_0x1016b3310;
+T_0 ;
+    %wait E_0x1016b3ac0;
+    %load/vec4 v0x1016b0fd0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0x1016b0f20_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x1016b0f20_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x1016b0f20_0, 0;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x1016b3190;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1016b97d0_0, 0, 1;
+T_1.0 ;
+    %delay 5000, 0;
+    %load/vec4 v0x1016b97d0_0;
+    %inv;
+    %store/vec4 v0x1016b97d0_0, 0, 1;
+    %jmp T_1.0;
+T_1.1 ;
+    %end;
+    .thread T_1;
+    .scope S_0x1016b3190;
+T_2 ;
+    %pushi/vec4 20260419, 0, 32;
+    %store/vec4 v0x1016b99b0_0, 0, 32;
+    %vpi_call/w 3 18 "$dumpfile", "simple_cpu_auto.vcd" {0 0 0};
+    %vpi_call/w 3 19 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1016b3190 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1016b9910_0, 0, 1;
+    %pushi/vec4 2, 0, 32;
+T_2.0 %dup/vec4;
+    %cmpi/s 0, 0, 32;
+    %jmp/1xz T_2.1, 5;
+    %jmp/1 T_2.1, 4;
+    %subi 1, 0, 32;
+    %wait E_0x1016b8ca0;
+    %jmp T_2.0;
+T_2.1 ;
+    %pop/vec4 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1016b9910_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1016b9870_0, 0, 32;
+T_2.2 ; Top of for-loop
+    %load/vec4 v0x1016b9870_0;
+    %cmpi/s 12, 0, 32;
+	  %jmp/0xz T_2.3, 5;
+    %wait E_0x1016b8ca0;
+T_2.4 ; for-loop step statement
+    %load/vec4 v0x1016b9870_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1016b9870_0, 0, 32;
+    %jmp T_2.2;
+T_2.3 ; for-loop exit label
+    %delay 1000, 0;
+    %vpi_call/w 3 27 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+    "N/A";
+    "<interactive>";
+    "-";
+    "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_out_cli/tb_simple_cpu_auto.v";
+    "/Users/ningyedong/Coding/Verilog-Learn/simple_cpu/simple_cpu.v";