Init Push

auto_batch/simple_cpu/simple_cpu_auto.vcd

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+$date
+	Sun Apr 19 14:24:11 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module tb_simple_cpu_auto $end
+$var reg 1 ! clk $end
+$var reg 1 " rst $end
+$var integer 32 # i [31:0] $end
+$var integer 32 $ seed [31:0] $end
+$scope module dut $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$var reg 4 % cnt [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+b0 %
+b1001101010010011001000011 $
+bx #
+1"
+0!
+$end
+#5000
+1!
+#10000
+0!
+#15000
+b1 %
+b0 #
+0"
+1!
+#20000
+0!
+#25000
+b10 %
+b1 #
+1!
+#30000
+0!
+#35000
+b11 %
+b10 #
+1!
+#40000
+0!
+#45000
+b100 %
+b11 #
+1!
+#50000
+0!
+#55000
+b101 %
+b100 #
+1!
+#60000
+0!
+#65000
+b110 %
+b101 #
+1!
+#70000
+0!
+#75000
+b111 %
+b110 #
+1!
+#80000
+0!
+#85000
+b1000 %
+b111 #
+1!
+#90000
+0!
+#95000
+b1001 %
+b1000 #
+1!
+#96000