Init Push

auto_batch/simple_cpu/auto_sim.out

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+#! /opt/homebrew/Cellar/icarus-verilog/13.0/bin/vvp
+:ivl_version "13.0 (stable)" "(v13_0)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 12;
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/system.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2005_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/va_math.vpi";
+:vpi_module "/opt/homebrew/Cellar/icarus-verilog/13.0/lib/ivl/v2009.vpi";
+S_0x1012a3bb0 .scope package, "$unit" "$unit" 2 1;
+ .timescale 0 0;
+S_0x1012a2190 .scope module, "tb_simple_cpu_auto" "tb_simple_cpu_auto" 3 2;
+ .timescale -9 -12;
+v0x1012a84e0_0 .var "clk", 0 0;
+v0x1012a8580_0 .var/i "i", 31 0;
+v0x1012a8620_0 .var "rst", 0 0;
+v0x1012a86c0_0 .var/i "seed", 31 0;
+E_0x1012a7830 .event posedge, v0x1012a0d80_0;
+S_0x1012a2310 .scope module, "dut" "simple_cpu" 3 9, 4 1 0, S_0x1012a2190;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+v0x1012a0d80_0 .net "clk", 0 0, v0x1012a84e0_0;  1 drivers
+v0x1012a0f70_0 .var "cnt", 3 0;
+v0x1012a8440_0 .net "rst", 0 0, v0x1012a8620_0;  1 drivers
+E_0x1012a2680 .event posedge, v0x1012a8440_0, v0x1012a0d80_0;
+    .scope S_0x1012a2310;
+T_0 ;
+    %wait E_0x1012a2680;
+    %load/vec4 v0x1012a8440_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0x1012a0f70_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x1012a0f70_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x1012a0f70_0, 0;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x1012a2190;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1012a84e0_0, 0, 1;
+T_1.0 ;
+    %delay 5000, 0;
+    %load/vec4 v0x1012a84e0_0;
+    %inv;
+    %store/vec4 v0x1012a84e0_0, 0, 1;
+    %jmp T_1.0;
+T_1.1 ;
+    %end;
+    .thread T_1;
+    .scope S_0x1012a2190;
+T_2 ;
+    %pushi/vec4 20260419, 0, 32;
+    %store/vec4 v0x1012a86c0_0, 0, 32;
+    %vpi_call/w 3 18 "$dumpfile", "simple_cpu_auto.vcd" {0 0 0};
+    %vpi_call/w 3 19 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x1012a2190 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x1012a8620_0, 0, 1;
+    %pushi/vec4 2, 0, 32;
+T_2.0 %dup/vec4;
+    %cmpi/s 0, 0, 32;
+    %jmp/1xz T_2.1, 5;
+    %jmp/1 T_2.1, 4;
+    %subi 1, 0, 32;
+    %wait E_0x1012a7830;
+    %jmp T_2.0;
+T_2.1 ;
+    %pop/vec4 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x1012a8620_0, 0, 1;
+    %pushi/vec4 0, 0, 32;
+    %store/vec4 v0x1012a8580_0, 0, 32;
+T_2.2 ; Top of for-loop
+    %load/vec4 v0x1012a8580_0;
+    %cmpi/s 8, 0, 32;
+	  %jmp/0xz T_2.3, 5;
+    %wait E_0x1012a7830;
+T_2.4 ; for-loop step statement
+    %load/vec4 v0x1012a8580_0;
+    %addi 1, 0, 32;
+    %store/vec4 v0x1012a8580_0, 0, 32;
+    %jmp T_2.2;
+T_2.3 ; for-loop exit label
+    %delay 1000, 0;
+    %vpi_call/w 3 27 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+# The file index is used to find the file name in the following table.
+:file_names 5;
+    "N/A";
+    "<interactive>";
+    "-";
+    "/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/tb_simple_cpu_auto.v";
+    "/Users/ningyedong/Coding/Verilog-Learn/simple_cpu/simple_cpu.v";

auto_batch/simple_cpu/sim_output.log

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+VCD info: dumpfile simple_cpu_auto.vcd opened for output.
+/Users/ningyedong/Coding/Verilog-Learn/slwchipverify/auto_batch/simple_cpu/tb_simple_cpu_auto.v:27: $finish called at 96000 (1ps)

auto_batch/simple_cpu/simple_cpu_auto.vcd

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+$date
+	Sun Apr 19 14:24:11 2026
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ps
+$end
+$scope module tb_simple_cpu_auto $end
+$var reg 1 ! clk $end
+$var reg 1 " rst $end
+$var integer 32 # i [31:0] $end
+$var integer 32 $ seed [31:0] $end
+$scope module dut $end
+$var wire 1 ! clk $end
+$var wire 1 " rst $end
+$var reg 4 % cnt [3:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+b0 %
+b1001101010010011001000011 $
+bx #
+1"
+0!
+$end
+#5000
+1!
+#10000
+0!
+#15000
+b1 %
+b0 #
+0"
+1!
+#20000
+0!
+#25000
+b10 %
+b1 #
+1!
+#30000
+0!
+#35000
+b11 %
+b10 #
+1!
+#40000
+0!
+#45000
+b100 %
+b11 #
+1!
+#50000
+0!
+#55000
+b101 %
+b100 #
+1!
+#60000
+0!
+#65000
+b110 %
+b101 #
+1!
+#70000
+0!
+#75000
+b111 %
+b110 #
+1!
+#80000
+0!
+#85000
+b1000 %
+b111 #
+1!
+#90000
+0!
+#95000
+b1001 %
+b1000 #
+1!
+#96000

auto_batch/simple_cpu/tb_simple_cpu_auto.v

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+`timescale 1ns/1ps
+module tb_simple_cpu_auto;
+
+    reg clk;
+    reg rst;
+    integer i;
+    integer seed;
+
+    simple_cpu dut (.clk(clk), .rst(rst));
+
+    initial begin
+        clk = 1'b0;
+        forever #5 clk = ~clk;
+    end
+
+    initial begin
+        seed = 20260419;
+        $dumpfile("simple_cpu_auto.vcd");
+        $dumpvars(0, tb_simple_cpu_auto);
+        rst = 1'b1;
+        repeat (2) @(posedge clk);
+        rst = 1'b0;
+        for (i = 0; i < 8; i = i + 1) begin
+            @(posedge clk);
+        end
+        #1;
+        $finish;
+    end
+endmodule